SBAA495A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 I2S and LJF Standard Bus Formats
    2. 3.2 Support for Non-Standard I2S and LJF Bus Formats
  6. 4Related Documentation
  7.   A Revision History

2.1 Controller Mode Configuration Options

TLV320ADCx120 and PCMx120-Q1 supports two functional modes when configured as an ASI controller:

  • Auto Clock Generation with Internal PLL enabled. Enabling the PLL allows the auto clock generator engine to generate a system clock that can be greater than the provided MCLK.
  • Auto Clock Generation with internal PLL disabled. Disabling the PLL limits the system clock to the MCLK frequency.

The system clock feeds the decimation filters and all the digital signal processing blocks (biquad filters, digital volume control, high pass filters, and so forth). Disabling the PLL limits the amount of digital signal processing available. However, with the low jitter PLL disabled, the performance of the ADC can be degraded based on the jitter from the external clock source. For devices configured as controller mode in high-performance applications, the recommended operating mode is to enable the PLL.

Configuring the TLV320ADCx120 and PCMx120-Q1 as an ASI controller requires that GPIO1 be configured as the MCLK input in GPIO_CFG0 (page 0, register 0x21, Bits 7-4). The frequency of MCLK must be one of the supported frequencies or ratios supported by configuring the MCLK_FREQ_SEL frequency selection mode (page 0, MST_CFG0 register 0x13, Bits 2-0), as shown in Table 2-1. Note that when using auto clock generation with internal PLL disabled, MCLK_RATIO_SEL (page 0, CLK_SRC register 0x16, bits 5-3) must also be configured.

Table 2-1 MCLK Frequency Selection Mode With Supported Frequencies or Ratios
MCLK FREQUENCY SELECTION MODESUPPORTED FREQUENCIES OR RATIOS
MCLK_FREQ_SEL (page 0, MST_CFG0 register 0x13, bits 2-0)12 MHz, 12.288 MHz, 13 MHz, 16 MHz, 19.2 MHz, 19.68 MHz,
24 MHz, 24.576 MHz
MCLK_RATIO_SEL (page 0, CLK_SRC register 0x16, bits 5-3)64, 256, 384, 512, 768, 1024, 1536, 2304