SBAA495A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 I2S and LJF Standard Bus Formats
    2. 3.2 Support for Non-Standard I2S and LJF Bus Formats
  6. 4Related Documentation
  7.   A Revision History

Supported Sample-Rates

Table 2-6 shows the supported sample-rates with the PLL disabled. As shown in Table 2-6, higher MCLK ratios allow the use of greater number or greater computation of digital processing blocks due to the greater availability of clocks in the system.

Table 2-6 Supported Sample Rates for Auto Clock Configuration With PLL Disabled
SAMPLING FREQUENCY (kHz) MCLK FREQUENCY(MHz) MCLK RATIO ADC CHANNELS DRE DECIMATION FILTERS BCLK RATIO WORD LENGTH
8 12.288 1536 1 Disabled Linear Phase 32 32
Low Latency
Ultra-Low Latency
2 Linear Phase 48 24
Low Latency
Ultra-Low Latency
16 12.288 768 1 Disabled Linear Phase 24 24
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled Ultra-Low Latency
2 Disabled Linear Phase 48
Low Latency
Ultra-Low Latency
16 24.576 1536 1 Disabled Linear Phase 24 24
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 48
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
16 36.864 2304 1 Disabled Linear Phase 24 24
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 48
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
24 12.288 512 1 Disabled Linear Phase 32 32
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 64 32
Ultra-Low Latency
24.576 1024 1 Disabled Linear Phase 32 32
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 64
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
24 36.864 1536 1 Disabled Linear Phase 24 24
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 48
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
32 12.288 384 1 Disabled Linear Phase 24 24
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 48
Ultra-Low Latency
24.576 768 1 Disabled Linear Phase 24
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 48
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
48 12.288 256 1 Disabled Linear Phase 32 32
Low Latency
Ultra-Low Latency
24.576 512 Linear Phase 32 32
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 64
Low Latency
Ultra-Low Latency
48 36.864 768 1 Disabled Linear Phase 24 24
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 48
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
96 24.576 256 1 Disabled Linear Phase 32 32
Low Latency
Ultra-Low Latency
36.864 384 Linear Phase 24 24
Enabled
Disabled Low Latency
Enabled
Disabled Ultra-Low Latency
Enabled
2 Disabled Linear Phase 48
Low Latency
Ultra-Low Latency