SBAA497B May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2. 1Introduction
  3. 2Infinite Impulse Response Filters
    1. 2.1 Digital Biquad Filter
  4. 3TLV320ADCx120 and PCMx120-Q1 Digital Biquad Filters
    1. 3.1 Filter Design Using PurePath Console
      1. 3.1.1 Example Generating Programmable Biquad Coefficients Using PurePath Console
    2. 3.2 How to Generate N0, N1, N2, D1, and D2 Coefficients with a Digital Filter Design Package
    3. 3.3 Avoid Overflow Conditions
    4. 3.4 Digital Biquad Filter Allocation to Output Channel
    5. 3.5 Programmable Coefficient Registers for Digital Biquad Filters 1–6
    6. 3.6 Programmable Coefficient Registers for Digital Biquad Filters 7–12
  5. 4How to Program the Digital Biquad Filters on the TLV320ADCx120 and PCMx120-Q1
  6. 5Typical Audio Applications for Biquad Filtering
    1. 5.1 Parametric Equalizers
  7. 6Crossover Networks
  8. 7Voice Boost
  9. 8Bass Boost
  10. 9Removing 50 Hz–60 Hz Hum With Notch Filters
  11.   A Digital Filter Design Techniques
    1.     A.A Analog Filters
  12.   B Related Documentation
  13.   B Revision History

3.4 Digital Biquad Filter Allocation to Output Channel

Table 3-2 shows the assignment of these biquad filters to a specific output channel based on the BIQUAD_CFG[1:0] register setting of the DSP_CFG1 register. Setting BIQUAD_CFG[1:0] to 2'b00 disables the Digital Biquad Filters for all channels. Select this setting when no additional filtering is needed for the system application. Table 3-2 also shows the mapping of the biquad filter coefficients in the TLV320ADCx120 and PCMx120-Q1 register space.

Table 3-2 Biquad Filter Allocation to the Record Output Channel
PROGRAMMABLE BIQUAD FILTERRECORD OUTPUT CHANNEL ALLOCATION USING DSP_CFG1 REGISTER SETTING
BIQUAD_CFG[1:0] = 2'b01
(1 BIQUAD PER CHANNEL)		BIQUAD_CFG[1:0] = 2'b10 (DEFAULT)
(2 BIQUADS PER CHANNEL)		BIQUAD_CFG[1:0] = 2'b11
(3 BIQUADS PER CHANNEL)
SUPPORTS ALL 4 CHANNELSSUPPORTS ALL 4 CHANNELSSUPPORTS ALL 4 CHANNELS
Biquad filter 1Allocated to output channel 1Allocated to output channel 1Allocated to output channel 1
Biquad filter 2Allocated to output channel 2Allocated to output channel 2Allocated to output channel 2
Biquad filter 3Allocated to output channel 3Allocated to output channel 3Allocated to output channel 3
Biquad filter 4Allocated to output channel 4Allocated to output channel 4Allocated to output channel 4
Biquad filter 5Not usedAllocated to output channel 1Allocated to output channel 1
Biquad filter 6Not usedAllocated to output channel 2Allocated to output channel 2
Biquad filter 7Not usedAllocated to output channel 3Allocated to output channel 3
Biquad filter 8Not usedAllocated to output channel 4Allocated to output channel 4
Biquad filter 9Not usedNot usedAllocated to output channel 1
Biquad filter 10Not usedNot usedAllocated to output channel 2
Biquad filter 11Not usedNot usedAllocated to output channel 3
Biquad filter 12Not usedNot usedAllocated to output channel 4

Table 3-3 shows the biquad filter coefficients mapping to the register space.

Table 3-3 Biquad Filter Coefficients Register Mapping
PROGRAMMABLE BIQUAD FILTERBIQUAD FILTER COEFFICIENTS REGISTER MAPPINGPROGRAMMABLE BIQUAD FILTERBIQUAD FILTER COEFFICIENTS REGISTER MAPPING
Biquad filter 1P2_R8-R27Biquad filter 7P3_R8-R27
Biquad filter 2P2_R28-R47Biquad filter 8P3_R28-R47
Biquad filter 3P2_R48-R67Biquad filter 9P3_R48-R67
Biquad filter 4P2_R68-R87Biquad filter 10P3_R68-R87
Biquad filter 5P2_R88-R107Biquad filter 11P3_R88-R107
Biquad filter 6P2_R108-R127Biquad filter 12P3_R108-R127

The DSP_CFG1 Register also determines the number of biquads used through the BIQUAD_CFG bit field shown in Figure 3-4 and Figure 3-5.

Figure 3-4 TLV320ADC3120 and PCM3120-Q1 DSP_CFG1 Register
76543210
DVOL_GANGBIQUAD_CFG[1:0]DISABLE_
SOFT_STEP		AGC_SELReserved

DRC_EN

EN_AVOID_CLIP

R/W-0hR/W-2hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Figure 3-5 TLV320ADC5120, TLV320ADC6120, PCM 5120-Q1 and PCM6120-Q1 DSP_CFG1 Register
76543210
DVOL_GANGBIQUAD_CFG[1:0]DISABLE_
SOFT_STEP		AGC_ DRE_AGC_SELReserved

DRC_EN

EN_AVOID_CLIP

R/W-0hR/W-2hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-4 DSP_CFG1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
7DVOL_GANGR/W0hDVOL control ganged across channels
0d = Each channel has its own DVOL CTRL settings as programmed in the CHx_DVOL bits
1d = All active channels must use the channel 1 DVOL setting (CH1_DVOL) irrespective of whether channel 1 is turned on or not
6-5BIQUAD_CFG[1:0]R/W2hNumber of biquads per channel configuration
0d = No biquads per channel; biquads are all disabled
1d = 1 biquad per channel
2d = 2 biquads per channel
3d = 3 biquads per channel
4DISABLE_SOFT_STEPR/W0hSoft-stepping disable during DVOL change, mute, and unmute
0d = Soft-stepping enabled
1d = Soft-stepping disabled
3AGC_SEL (TLV320ADC3120
and PCM3120-Q1)		R/W0hAGC selection when is enabled for any channel.
0d = AGC is not selected
1d = AGC is selected
DRE_AGC_SEL (TLV320ADC5120,
TLV320ADC6120,
PCM5120-Q1,
and PCM6120-Q1)		DRE or AGC selection when is enabled for any channel.
0d = DRE is selected
1d = AGC is selected
2ReservedR/W0hReserved

1

DRC_EN

R/W

0h

Dynamic range compression (DRC) same as DRE without gain compensation in digital
0d = DRC disabled. Device can be in DRE or AGC mode depending on DRE_AGC_SEL bit
1d = 1 DRC enabled. Device cannot be in DRE or AGC mode.

0

EN_AVOID_CLIP

R/W

0h

Anti-clipper when channel gain > 0 dB and either of DRE, DRC or AGC mode enabled.
0d = Channel gain is maintained as per user programmed channel gain value
1d = Signal level is compressed to avoid clipping when channel gain > 0 dB and the signal level crosses the programmed threshold setting set in page-4.