3 What’s New in JESD204C

There are many enhancements in the C revision of the standard; many of the enhancements improve coding efficiency and overall throughput. JESD204C is backward-compatible with the A and B standards, but with some limitations in subclass-0 operation. Designers familiar with the JESD204B revision will see compatibility based on the coding scheme and recommendations for higher throughput, using various enhancements to the standard.

The most obvious change is the addition of denser 64B/66B and 64B/80B coding schemes; these methods are far more efficient in symbol coding. 64B/66B has only a 3.125% coding overhead versus the 20% overhead on 8B/10B. The downside is that it initially takes longer to encode due to the longer symbol length, which will result in a certain coding latency since most data converters provide 8 to 16 bits of data per sample.

For 8B/10B, not much has changed from the B revision. Subclass 0, 1 and 2 are all supported. As a refresher, subclass 0 is the A revision’s backward-compatibly mode, used for the lowest possible link delay without deterministic latency. Subclasses 1 and 2 establish deterministic channel latency and multi-device phase alignment. The transport still uses the SYNC interface and initial lane alignment sequence (ILAS) to establish both data alignment and channel latency.

The 64B/66B and 64B/80B coding standards used in JESD204C are a bit more complicated and no longer use the ILAS and SYNC interface to establish proper frame alignment. Instead, these modes use a SYNC header embedded as the first 2 bits of every frame, which are concatenated into a 32-bit SYNC message. Every run of 66 bits starts with the sync header symbol (2 bits – 01 or 10 are valid sync symbols, 00 and 11 are illegal values) encoded into the SYNC header stream. This stream always contains a pilot signal used for sync alignment to the 66-bit frame. Multiple frames form blocks, and groups of blocks form extended multi-blocks. Once the receiver identities where in the stream the SYNC resides, it then moves on to identify where the frames are aligned by using the last frame indicator in the stream to sync to the frame boundaries.

Beyond the coding, there are several new classes of data transmitters and receivers that help the transmission speed and lower the interface power. These classes are shown in Table 3-1.

The three new revision C classes allow device manufacturers to provide driver/receiver pairs that have varying amounts of signal integrity processing to reduce power in shorter channels. For example, the C-S class requires that the receiver’s continuous time linear equalizer (CTLE) have only 6 dB of gain and no decision feedback equalization (DFE). Class C-R, however, requires that the CTLE have a minimum of 12 dB of gain and a 14-tap DFE. So manufacturers can provide modes that support all classes and give designers the flexibility to choose the best mode for the channel.

In addition to using SYSREF in subclass 1 for phase alignment, the latest revision introduces a new signal called MULTIREF. Unlike the SYSREF signal, which originates in clocking devices, MULTIREF is an output from the data converter and is fed to the SYSREF input of the next data converter. Because the signal originates from the data converter, it may be difficult to meet the setup and hold times of some devices. Where applicable, however, the MULTIREF signal can greatly simplify the clocking of multiple converters where frame alignment is required but deterministic latency is not.

Table 3-2 lists the most significant differences between the two standards. Higher data rates are a significant difference; to better support them, there are two new coding schemes. The methods for synchronization vary by these coding schemes, and there is some additional complexity to this process.