SBAA528 February   2022 ADC12QJ1600-Q1 , TPS62912 , TPS62913

 

  1.   Trademarks
  2. 1Introduction and System Description
    1. 1.1 Introduction
      1. 1.1.1 ADC12QJ1600-Q1 Noise and Ripple Requirements
      2. 1.1.2 Power Supply Requirements for Clocks
      3. 1.1.3 TPS62913 Low-Noise and Low-Ripple Buck Converter
    2. 1.2 Block Diagram
    3. 1.3 Design Considerations
  3. 2Tests and Results
    1. 2.1 Test Methodology
    2. 2.2 Test Conditions
    3. 2.3 Test Results
  4. 3Conclusion
  5. 4References
  6.   A Appendix

1.1 Introduction

High speed analog to digital converters are notoriously sensitive to power supply noise. The most common solution to minimize that noise is to use linear power supplies, or a switch mode power supply (SMPS) from the main bus rail followed by a low dropout regulator. Compared to a linear supply, there are two big advantages of being able to use a SMPS alone: the reduction in power loss and the size of the power supply. To use a SMPS alone requires careful consideration of the switching supply selected, as well as the design and layout of the SMPS to achieve the desired results of the same performance with lower power dissipation and smaller board space.

This application note uses the ADC12QJ1600-Q1 as an example of a high performance ADC where the supplies have been changed from a SMPS+LDO approach to a SMPS-only approach. This methodology can be used for many other noise sensitive applications as well. The TPS62913 low-ripple and low-noise buck converter used in this application note is specifically designed to help engineers design power supplies that meet the noise and ripple requirements for noise sensitive applications.