SBAA528 February 2022 ADC12QJ1600-Q1 , TPS62912 , TPS62913
The original ADC12QJ1600-Q1 Rev A evaluation module used several SMPS with LDO followers to provide power to the ADC and clock rails. The 3.3 V clock rails require low phase noise and low jitter. The 1.1 V analog rail (VA11) and digital rail (VD11) are supplied through one LDO and each rail is split with a feed through filter capacitor to ensure low noise requirements for both analog and digital rails. The 1.9 V supplies are also supplied through one LDO with each rail having a split that connects to a feed through filter capacitor as shown in Figure 1-4.
The original EVM power supply is outlined in blue and shown in Figure 1-5.
In the revised design, the LDOs are removed and the TPS62913 low-ripple, low-noise SMPS is used instead. This design presents a simplified power supply network for the ADC, where all three power domains are supplied from a DC/DC regulator as shown in Figure 1-6. This implementation improves the efficiency and reduces the part count in comparison to a solution using LDOs while maintaining the output voltage ripple and noise requirements of the ADC and clock for good performance.
The updated EVM power supply with the TPS62913 is outlined in blue and shown in Figure 1-7.
The schematics for the 3.3-V, 1.1-V, and 1.9-V rails can be found in the Section A.
Component | Original Rev C | Rev C with TPS62913 |
---|---|---|
Switching Power Supplies | 3 x LMS3635M (4mm x 5mm ea) | 3 x TPS62913 (2mm x 2mm ea) |
LDO's | 3 x TPS7A8400 (3.5mm x 3.5mm ea) | None |
Size of Power Supplies | 96.75 sqmm + passives | 12 sqmm + passives |