SBAA531 November   2021 ADS8860 , ADS8862 , ADS8881 , ADS9110 , ADS9224R

 

  1.   Trademarks
  2. 1Introduction
  3. 2 Internal Topology of SAR ADC Model
    1. 2.1  Sample and Hold
    2. 2.2  Sample and Hold Timing
    3. 2.3  Reference Transients
    4. 2.4  Bandwidth Modeling
    5. 2.5  Noise Modeling
    6. 2.6  Reference Droop and Reference Noise Errors
    7. 2.7  Gain, Offset, and Input Leakage Modeling
    8. 2.8  Differential input behavior
    9. 2.9  ESD Protection Diodes and Parasitic Capacitance
    10. 2.10 Summary of Parameters
    11. 2.11 Summary of Model Pins
  4. 3Downloading and Using PSpice® Example Projects From Web
    1. 3.1 Selecting the Amplifier and Optimizing the RC Circuit
    2. 3.2 Worst-Case Settling by Adjusting the Reset Capacitor
    3. 3.3 Verification of Reference Droop
    4. 3.4 System Noise Verification
    5. 3.5 Gain, Offset, and Input Leakage Verification
  5. 4Summary

2.11 Summary of Model Pins

Table 2-2 lists a short summary of the model pin. For more details on the pins and internal model schematics, see the previous sections of this application report.

Table 2-2 Model Pin Summary
Pin NamePin Function
INNNegative analog input pin for the device.
INPPositive analog input pin for the device
VrefExternal reference input pin for the device. Connect the external Vref here.
SampleRateThis pin controls the sampling rate of the ADC. Connect a ±5-V square wave here. Set the frequency of that square wave to the sampling rate at which the device must operate. So, for a 1 Msps device, apply a 1-MHz, ±5-V square wave.
Vref_idealConnect this pin to the ideal value of the voltage reference. If left unconnected it floats to the value of the VREF parameter in the parameter list. So, for example, the ADS8860 has the VREF parameter set to 5 V. If using a nominal 5-V reference, do not connect this pin. This pin calculates the effects of reference droop and reference error in the output signals.
Vref_errThis is an output pin used to show the reference error. If this output is 0 V there is no error on the output. If the output is 1 mV, the reference has a 1-mV error.
Vsettling errorThis is an output pin used to show the effects of sample and hold settling. This pin compares the steady state ideal input to the ADC to the sample and hold value captured for Vref. If Vsettling_error = 1 mV, than the settling error is 1 mV. Note settling is tested with a DC input signal. This output is not meaningful for AC inputs.
VsampShows the output of the sample and hold.
TacqThis is an internal signal that shows when the ADC is acquiring (sampling).
TCONVThis is an internal signal that shows when the ADC is converting (holding).
ResetSHThis is an internal signal that illustrates when the internal sample and hold is reset.