SBAA576A may   2023  – june 2023 ADS54J60

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Interleaving Architecture
  6. 3DC Offset Correction
    1. 3.1 DC Offset Correction Architecture
      1. 3.1.1 Default Configuration
      2. 3.1.2 Bypassing the DC Offset Correction
    2. 3.2 Freezing the DC Offset Correction
    3. 3.3 Effect of Environmental Temperature Fluctuations
    4. 3.4 Effect of Input Frequency on Interleaving Spur
  7. 4External Offset Correction
  8. 5Configuring External DC Offset Correction (Channel A)
    1. 5.1 Device Default Configuration
    2. 5.2 Baseline HSDC Pro Capture
    3. 5.3 Freezing the Interleaving Engine and DC Offset Values
    4. 5.4 Reading the Frozen DC Offset Values
    5. 5.5 Loading the DC Offset Values
    6. 5.6 Confirm HSDC Pro Capture
  9. 6Summary
  10. 7References
  11. 8Revision History

2 Interleaving Architecture

Figure 2-1 highlights the area of interest within the part containing the DC offset correction feature. The four internal interleaved ADC cores in each channel can sample up to 250 MSPS, resulting into an output data stream of up to 1 GSPS (or Nyquist bandwidth of 500 MHz).

The amplifier in the first pipeline stage increases the DC offset mismatch between the cores and generates higher interleaving spurs. The spur at DC arises due to the average offset of the four cores. To reduce the mismatch between cores, each interleaved ADC core has an individual DC offset correction block that aims to bring the core offset to a mid-code value. The corrected data from each core is then combined into the interleaving engine block.

GUID-20230428-SS0I-GG3J-KP5X-V7TWSCLC0MWS-low.svg Figure 2-1 Functional Block Diagram