SBAA576A may   2023  – june 2023 ADS54J60

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Interleaving Architecture
  6. 3DC Offset Correction
    1. 3.1 DC Offset Correction Architecture
      1. 3.1.1 Default Configuration
      2. 3.1.2 Bypassing the DC Offset Correction
    2. 3.2 Freezing the DC Offset Correction
    3. 3.3 Effect of Environmental Temperature Fluctuations
    4. 3.4 Effect of Input Frequency on Interleaving Spur
  7. 4External Offset Correction
  8. 5Configuring External DC Offset Correction (Channel A)
    1. 5.1 Device Default Configuration
    2. 5.2 Baseline HSDC Pro Capture
    3. 5.3 Freezing the Interleaving Engine and DC Offset Values
    4. 5.4 Reading the Frozen DC Offset Values
    5. 5.5 Loading the DC Offset Values
    6. 5.6 Confirm HSDC Pro Capture
  9. 6Summary
  10. 7References
  11. 8Revision History

5.4 Reading the Frozen DC Offset Values

The DC offset correction values are setup to be read and recorded. Using the ADS54JXX GUI, navigate to the ‘Low Level View’ tab. Select the ADS54Jxx_LowLevel block. The 11-bit DC offset correction values can be read and recorded from addresses 0xE074 through 0xE07B for Channel A, and from 0xF074 through 0xF07B for Channel B.

GUID-20230502-SS0I-48KJ-4LK1-RKJXWM72PBRL-low.png Figure 5-3 ADS54J60 GUI Register R/W Feature
Table 5-1 Recorded Frozen DC Offset Values
Address (CHA) DC Offset Correction Value
(this example)		 Address (CHB) DC Offset Correction Value
0xE074 0x27 0xF074 (value)
0xE075 0x07 0xF075 (value)
0xE076 0x3A 0xF076 (value)
0xE077 0x07 0xF077 (value)
0xE078 0xCC 0xF078 (value)
0xE079 0x00 0xF079 (value)
0xE07A 0xCC 0xF07A (value)
0xE07B 0x00 0xF07B (value)