SBAA576A may   2023  – june 2023 ADS54J60

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Interleaving Architecture
  6. 3DC Offset Correction
    1. 3.1 DC Offset Correction Architecture
      1. 3.1.1 Default Configuration
      2. 3.1.2 Bypassing the DC Offset Correction
    2. 3.2 Freezing the DC Offset Correction
    3. 3.3 Effect of Environmental Temperature Fluctuations
    4. 3.4 Effect of Input Frequency on Interleaving Spur
  7. 4External Offset Correction
  8. 5Configuring External DC Offset Correction (Channel A)
    1. 5.1 Device Default Configuration
    2. 5.2 Baseline HSDC Pro Capture
    3. 5.3 Freezing the Interleaving Engine and DC Offset Values
    4. 5.4 Reading the Frozen DC Offset Values
    5. 5.5 Loading the DC Offset Values
    6. 5.6 Confirm HSDC Pro Capture
  9. 6Summary
  10. 7References
  11. 8Revision History

3.1.2 Bypassing the DC Offset Correction

The DC offset corrector cannot distinguish the external DC signal from internal DC offset for applications that use an amplifier driver to dc-couple to the ADC. This feature, shown in Figure 3-1, can be bypassed through SPI. Bypassing results in a histogram with multi-modal output codes and interleaving spurs as large as -40 dBFS in the spectrum at DC, fs/4, and fs/2.

GUID-20230428-SS0I-KHW5-SXZB-S0HZTFXLWM6F-low.svgFigure 3-1 DC Offset Corrector Architecture (one ADC Core)