SBAA576A may   2023  – june 2023 ADS54J60

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Interleaving Architecture
  6. 3DC Offset Correction
    1. 3.1 DC Offset Correction Architecture
      1. 3.1.1 Default Configuration
      2. 3.1.2 Bypassing the DC Offset Correction
    2. 3.2 Freezing the DC Offset Correction
    3. 3.3 Effect of Environmental Temperature Fluctuations
    4. 3.4 Effect of Input Frequency on Interleaving Spur
  7. 4External Offset Correction
  8. 5Configuring External DC Offset Correction (Channel A)
    1. 5.1 Device Default Configuration
    2. 5.2 Baseline HSDC Pro Capture
    3. 5.3 Freezing the Interleaving Engine and DC Offset Values
    4. 5.4 Reading the Frozen DC Offset Values
    5. 5.5 Loading the DC Offset Values
    6. 5.6 Confirm HSDC Pro Capture
  9. 6Summary
  10. 7References
  11. 8Revision History

5.3 Freezing the Interleaving Engine and DC Offset Values

The required low-level register writes to freeze and read the DC offset values are compiled into the following files. These three configuration files address the required 500 ms delay after setting the DC calibration bandwidth, freezing the interleaving calibration engine, and freezing the DC correction value.

  1. DC Calibration Bandwidth: DC_IL_Freeze1.cfg
    1. Sets the DC calibration bandwidth for both channels to 5 (or 9 Hz)
    2. This increases the accuracy of the estimated DC offset value
  2. Freeze Interleaving Engine: DC_IL_Freeze2.cfg
    1. Enables the interleaving block freeze/unfreeze option
    2. Freezes the interleaving calibration engine
  3. Freeze DC Offset Correction Block: DC_IL_Freeze3.cfg
    1. Freezes DC offset correction block for both channels
    2. Enables a single channel register write (reads the values from each individual channel; otherwise, the frozen values will be incorrectly read back)