SBAA583 july 2023 PCM1820 , PCM1820-Q1 , PCM1821 , PCM1821-Q1 , PCM1822 , PCM1822-Q1 , PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120
Figure 2-1 describes the equivalent circuit for the input pin. In a capacitive coupled system, the biasing of the pin is done internally by the voltage as shown in Equation 1, where k is approximately 0.5.
Register settings for the input pin:
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH1_INTYP | R/W | 0h | Channel 1 input type 0d = Microphone input 1d = Line input |
6-5 | CH1_INSRC[1:0] | R/W | 0h | Channel 1 input configuration 0d = Analog differential input (the GPI1 and GPO1 pin functions must be disabled) 1d = Analog single-ended input (the GPI1 and GPO1 pin functions must be disabled) 2d = Digital microphone PDM input (configure the GPO and GPI pins accordingly for PDMDIN1 and PDMCLK) 3d = Reserved |
4 | CH1_DC | R/W | 0h | Channel 1 input coupling (applicable for the analog input) 0d = AC-coupled input 1d = DC-coupled input |
3-2 | CH1_IMP[1:0] | R/W | 0h | Channel 1 input impedance (applicable for the analog input) 0d = Typical 2.5-kΩ input impedance 1d = Typical 10-kΩ input impedance 2d = Typical 20-kΩ input impedance 3d = Reserved |
1 | Reserved | R | 0h | Reserved |
0 | CH1_DREEN | R/W | 0h | Channel 1 dynamic range enhancer (DRE) and automatic gain controller (AGC) setting 0d = DRE and AGC disabled 1d = DRE or AGC enabled based on the configuration of bit 3 in register 108 (P0_R108) |
P0_R59_D[1:0] : ADC_FSCALE[1:0] | VREF Output Voltage (Same as Internal ADC VREF) | Differential Full-Scale Input Supported | Single-Ended Full-Scale Input Supported | AVDD Range Requirement |
---|---|---|---|---|
00 (default) | 2.75 V | 2 VRMS | 1 VRMS | 3 V to 3.6 V |
01 | 2.5 V | 1.818 VRMS | 0.909 VRMS | 2.8 V to 3.6 V |
10 | 1.375 V | 1 VRMS | 0.5 VRMS | 1.7 V to 1.9 V |
11 | Reserved | Reserved | Reserved | Reserved |
P0_R60_D[3:2] : CH1_IMP[1:0] | Channel 1 Input Impedance Selection |
---|---|
00 (default) | Channel 1 input impedance typical value is 2.5 kΩ on INxP or INxM |
01 | Channel 1 input impedance typical value is 10 kΩ on INxP or INxM |
10 | Channel 1 input impedance typical value is 20 kΩ on INxP or INxM |
11 | Reserved (do not use this setting) |