SBAA600 October   2024 TAA5212 , TAC5111 , TAC5112 , TAC5211 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Voice Activity Detection
    1. 2.1 VAD Configurations
      1. 2.1.1 User, Auto, Intermediate
      2. 2.1.2 VAD With ADC Recording
      3. 2.1.3 VAD Monitoring Channel
      4. 2.1.4 VAD Interrupt Pin
      5. 2.1.5 MICBIAS Enable During PDM Monitoring
      6. 2.1.6 VAD Clock Configurabilty
    2. 2.2 VAD Parameters
      1. 2.2.1 Initial Learning Period
      2. 2.2.2 Hold Over Counter
      3. 2.2.3 Wakeup Wait
      4. 2.2.4 Threshold
  6. 3VAD Performance Results
  7. 4Examples
  8. 5Summary
  9. 6References

2.1.6 VAD Clock Configurabilty

VAD can be run on either the internal oscillator clock or the external clock provided by the user. This external clock can be given on either the BCLK pin or the MCLK pin.

As Table 2-8 shows, VAD clock selection is done using the LPAD_LPSG_CLK_CFG[1:0] bit of LPAD_LPSG_CFG1[7:6] register (page = 0x01, address = 0x20).

If the user selects either 1d or 2d, then the frequency of external clock is selected using LPAD_LPSG_EXT_CLK_CFG[1:0] bit of LPAD_LSG_CFG1[5:4] register (page = 0x01, address = 0x20) as shown in Table 2-9.

Table 2-8 VAD Clock Selection Using LPAD_LPSG_CFG1 Register
Bit Field Type Reset Description
7-6 VAD_CLK_CFG[1:0] R/W 00b Clock select for VAD
0d = VAD processing using internal oscillator clock
1d = VAD processing using external clock on BCLK input
2d = VAD processing using external clock on MCLK input
3d = Custom clock configuration based on MST_CFG, CLK_SRC and CLKGEN_CFG registers in page 0
Table 2-9 VAD Clock Frequency Selection Using LPAD_LPSG_CFG1 Register
Bit Field Type Reset Description
5-4 VAD_EXT_CLK_CFG[1:0] R/W

00b

 Clock configuration using external clock for VAD.
0d = External clock is 3.072MHz
1d = External clock is 6.144MHz
2d = External clock is 12.288MHz
3d = External clock is 18.432MHz