This section describes the typical current consumption of the TAC511x when the PLL is disabled with AVDD set to 1.8V and 3.3V.

The PLL is disabled by setting the corresponding bit fields, B0_P0_R52[7] (PLL_DIS) and LOW_PWR_FILT, which must be enabled for both ADC and DAC (ADC_LOW_PWR_FILT and DAC_LOW_PWR_FILT), and B0_P0_R78[2] and B0_P0_R79[2], respectively.

By default, the bit clock is used as the clock source when the PLL is disabled. Alternatively, an external clock source (CCLK) can be used in the device through one of the GPI-capable pins (GPIOx/GPIx), if the system has a low jitter clock available.

• If GPIOx is used for the CCLK input, the appropriate GPIOx_CFG bit field in the GPIOx_CFG0 register must be configured for GPI function.
• If GPIx is used for the CCLK input, the appropriate GPIx_CFG bit field in the GPI_CFG register must be enabled for GPI function.
• The pin configured for GPI must be configured as CCLK, this is done by configuring B0_P0_R15[6:5] (CCLK_SEL), based on the configured pin.
• With the CCLK configured, the external CCLK must be used as the clock source, instead of BCLK, this is done by configuring B0_P0_R52[3:1] (CLK_SRC_SEL).
• Once configured, the device runs the external CCLK as the clock source.

In Table 3-4, the power consumption measurements have the biquad filters disabled, the DAC and ADC are both in idle channel, the ADC is in a full differential input setting, and an external CCLK of 12.288MHz is used as the device clock source through the GPIO1 pin.