Biasing power amplifiers (PA) in aerospace and defense applications can be expensive, hard to scale, and require a large area of board space to implement. The AFE20408 addresses these issues by integrating eight digital-to-analog converters (DACs), an analog-to-digital converter (ADC), and fast gate bias switches into a small 5mm x 5mm package. This application note also details power-on sequencing requirements and the multiple output configurations of the AFE20408.
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The AFE20408 is an analog front end (AFE) highly integrated PA biasing controller. The AFE combines 8 DACs, a multi-input ADC, and fast gate bias switches in a tiny 5mm x 5mm package.
The eight 13-bit DACs each have a range of 0V to 10V and –10V to 0V. The DACs are grouped in two blocks, each with a separate supply voltage. This allows for both positive and negative DAC outputs on one device, enabling one device to power both LDMOS and GaN PAs.
The AFE20408 has two groups of four fast low on-resistance switched outputs. These switched outputs allow for fast switching between two DAC channels at different voltages facilitating time-division duplexing. These switched outputs can also switch from a DAC voltage to VSS, allowing more DAC channels to be used for gate biasing. Built in redundancy allows the switches to be toggled either through software bits or hardware pins.
The AFE20408 features an integrated 16-bit ADC. The ADC has two high-voltage bus lines that measure voltages up to an 85V input and two pairs of high-side current sense inputs. Furthermore, the device has an internal temperature sensor. All of these inputs can be configured to set an alarm condition with user-defined minimum and maximum thresholds.
Other features of the AFE20408 include a flexible digital VIO voltage input from 1.8V to 5V, an auto-detectable SPI or I2C communication interface, sixteen I2C target addresses, a device-good pin (PAON) to indicate device readiness, and a FLEXIO pin that can be configured as RESET, ALARMOUT, ALARMIN, LDAC, DRVEN2, or a GPIO pin.
Figure 2-1 shows an example application of the AFE20408.
The application figure highlights how to use the various features of the AFE20408:
The PAON switch keeps the PAVDD isolated through a high voltage NMOS-PMOS switch. When PAON is low, the PMOS is disabled and the PAVDD is isolated from the PA. When PAON is high, the PMOS is enabled and the PAVDD is connected to the PA. By default, the PAON pin is low and requires the user to enable. This circuit ensures that the PA is isolated and protected during startup.
The ADC has user configurable alarm conditions used to monitor the PAVDD voltage and current. The ADCHV channels can alert the system if the PAVDD voltage is measured out of the configured thresholds and the SENSE pins can be configured with an external resistor to monitor PAVDD current. If the ADC detects an alarm condition, the PAON and DAC outputs shut off to protect the PA.
The fast switching works via capacitor charge sharing. The DAC outputs have large external capacitance while the OUT outputs have small external capacitance. When the switch toggles between different outputs, the small capacitor on the output is quickly charged by the larger DAC capacitor, allowing for very fast output switching. The output slews to 95% of the DAC voltage within 100ns. The switches have a max 400ns activation time.