2 Application Figure

Figure 2-1 shows an example application of the AFE20408.

Figure 2-1 AFE20408 GaN and LDMOS PA Biasing Application

The application figure highlights how to use the various features of the AFE20408:

The PAON switch keeps the PAVDD isolated through a high voltage NMOS-PMOS switch. When PAON is low, the PMOS is disabled and the PAVDD is isolated from the PA. When PAON is high, the PMOS is enabled and the PAVDD is connected to the PA. By default, the PAON pin is low and requires the user to enable. This circuit ensures that the PA is isolated and protected during startup.

The ADC has user configurable alarm conditions used to monitor the PAVDD voltage and current. The ADCHV channels can alert the system if the PAVDD voltage is measured out of the configured thresholds and the SENSE pins can be configured with an external resistor to monitor PAVDD current. If the ADC detects an alarm condition, the PAON and DAC outputs shut off to protect the PA.

The fast switching works via capacitor charge sharing. The DAC outputs have large external capacitance while the OUT outputs have small external capacitance. When the switch toggles between different outputs, the small capacitor on the output is quickly charged by the larger DAC capacitor, allowing for very fast output switching. The output slews to 95% of the DAC voltage within 100ns. The switches have a max 400ns activation time.