SBAA637 June   2024 AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 SPI Failure During Bring-Up
    1. 2.1 Detail Regarding Chip Readouts
    2. 2.2 Failure and Fix for Chip Read Check
    3. 2.3 Poll Check for SPI Access for PLL Page
    4. 2.4 Failure and Fix for the SPI Poll Check for PLL Page Access
    5. 2.5 Read Check Indicating Status of Fuse Farm Autoload
    6. 2.6 Failure and Fix for Autoload Read Check
  6. 3 Macro Failure Breaking the Bring-Up Flow
    1. 3.1 Read Check for Macro Error and Poll Check for Macro Done
    2. 3.2 Failure and Fix for Macro Error and Poll check for Macro Done
  7. 4 AFE PLL Failure
    1. 4.1 Read Check for PLL Lock
    2. 4.2 Failure and Fix for Read Check of PLL
  8. 5 AFE Internal Sysref Flag Failure
    1. 5.1 Read Check Status of Sysref Flag Bit
    2. 5.2 Failure and Fix for Read Check Status of Sysref Flag Bit
  9. 6 JESD Link Check Failure
    1. 6.1 Multiple Read Checks Indicating Status of JESD Linkup
    2. 6.2 Failure and Fix for JESD Error
  10. 7 Validating Serdes and JESD Link using CAPI
    1. 7.1 Useful Serdes Debug CAPIs
    2. 7.2 Useful JESD Debug CAPIs
  11. 8 TX Chain Validation
  12. 9 RX Chain Validation
  13. 10Device Health
  14. 11Summary
  15. 12References

4.1 Read Check for PLL Lock

PLL Lock status is read to check if device main PLL is locked and is stable.

SPIReadCheck 0066,4,4,10	//Lock
SPIReadCheck 0066,6,6,00	//Lock Lost Sticky

We monitor two specific bits, Bit[4] signifies current Lock status of PLL, while Bit[6] indicates whether PLL lost lock after being lock for first time. This bit indicates instability in PLL after the first time it has locked.

Table 4-1 Reference Clock Electrical Characteristics
fPFD PFD frequency 100 500 MHz
FREF Input Clock frequency 0.1 12 GHz
VSS Input Clock level 0.6 1.8 VPPdiff
Coupling AC Coupling Only
REFCLK input impedance Parallel resistance 100 Ω
Parallel capacitance 0.5 pF