SBAA637 June   2024 AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 SPI Failure During Bring-Up
    1. 2.1 Detail Regarding Chip Readouts
    2. 2.2 Failure and Fix for Chip Read Check
    3. 2.3 Poll Check for SPI Access for PLL Page
    4. 2.4 Failure and Fix for the SPI Poll Check for PLL Page Access
    5. 2.5 Read Check Indicating Status of Fuse Farm Autoload
    6. 2.6 Failure and Fix for Autoload Read Check
  6. 3 Macro Failure Breaking the Bring-Up Flow
    1. 3.1 Read Check for Macro Error and Poll Check for Macro Done
    2. 3.2 Failure and Fix for Macro Error and Poll check for Macro Done
  7. 4 AFE PLL Failure
    1. 4.1 Read Check for PLL Lock
    2. 4.2 Failure and Fix for Read Check of PLL
  8. 5 AFE Internal Sysref Flag Failure
    1. 5.1 Read Check Status of Sysref Flag Bit
    2. 5.2 Failure and Fix for Read Check Status of Sysref Flag Bit
  9. 6 JESD Link Check Failure
    1. 6.1 Multiple Read Checks Indicating Status of JESD Linkup
    2. 6.2 Failure and Fix for JESD Error
  10. 7 Validating Serdes and JESD Link using CAPI
    1. 7.1 Useful Serdes Debug CAPIs
    2. 7.2 Useful JESD Debug CAPIs
  11. 8 TX Chain Validation
  12. 9 RX Chain Validation
  13. 10Device Health
  14. 11Summary
  15. 12References

6.2 Failure and Fix for JESD Error

  1. If there is error in 0x118 or 0x119, this is serdes related error reg so it is important to check signal integrity of serdes. We have CAPI to check for PRBS test pattern in SRX and read the error counter.

    CAPI for SRX PRBS checker:

    enableSerdesRxPrbsCheck

    clearSerdesRxPrbsErrorCounter

    getSerdesRxPrbsError

    Also, if you want to verify the signal integrity for AFE to FPGA connection for serdes PHY layer, AFE had CAPI to send PRBS pattern.

    CAPI for STX PRBS enable:

    sendserdesTxPrbs

  2. Other reg, 0x11b, 0x11c, 0x11d, 0x11e and 0x11f are JESD Lane error indicator. The error bit and the description are self-explanatory to indicate the issue in JESD Link. The following is a list of some common error and design for errors.

JESD204B

  1. Using Subclass 1, make sure Sysref is correctly acknowledge by both AFE and FPGA/ASIC in deterministic fashion. Must be source synchronous with Device Clock and FPGA Ref. Clock, rising edge transition determines LMFC alignment.
    Deterministic Latency Figure 6-1 Deterministic Latency

  2. Lower serdes eye margin can cause issue, Try to adjust FFE Taps from FPGA/ASIC to improve swing of SRX on AFE.
  3. Send K28.5 pattern from FPGA and Check if the AFE SYNC PIN is responding and check if CS state is as expected.
  4. If we see any alignment related error there is a need to adjust RBD value. RBD is a release buffer space to buffer data for the time to adjust latency variation of lanes. See the Determining Optimal Receive Buffer Delay in JESD204B and JESD204C Receivers, application note.
  5. After RBD is set correctly, FS state also becomes correct and link is stable at this point.
  6. Check serdes polarity. If serdes polarity is reversed, CS state can come but FS and Buff state can not come.
  7. Check if the 204B scrambler status matches for AFE and FPGA/ASIC. Either both can be enabled or both can be disabled.

JESD204C

  1. As mentioned previously, sysref can be synchronized and applied in deterministic fashion for AFE and FPGA/ASIC.
  2. Lower serdes eye margin can cause issue, try to adjust FFE Taps from FPGA/ASIC to improve swing of SRX on AFE.
  3. Major source of alignment error in 204C is due to incorrect RBD size. So refer to how to set RBD application note for same.(Determining Optimal Receive Buffer Delay in JESD204B and JESD204C Receivers).
  4. Depending on resolution of sample if 16 bits choose Extended Multiblock E = 1, if resolution is 12/24 bits choose E=3.
  5. Choose CRC mode same for JESD receiver and transmitter.
  6. Check serdes polarity. If serdes polarity is reversed, none of the CS, Buff and FS state comes.