Table 7. PGA Full-Scale Range

9.3.2.1 PGA Common-Mode Voltage Requirements

To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are discussed in this section.

The outputs of both amplifiers (A1 and A2) in Figure 52 can not swing closer to the supplies (AVSS and AVDD) than 100 mV. If the outputs OUT_P and OUT_N are driven to within 100 mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition, the output voltages must meet Equation 5.

Translating the requirements of Equation 5 into requirements referred to the PGA inputs (AIN_P and AIN_N) is beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design; therefore, the common-mode voltage at the output of the PGA can be assumed to be the same as the common-mode voltage of the input signal, as shown in Figure 53.

Figure 53. PGA Common-Mode Voltage

The common-mode voltage is calculated using Equation 6.

The voltages at the PGA inputs (AIN_P and AIN_N) can be expressed as Equation 7 and Equation 8.

The output voltages (V_(OUTP) and V_(OUTN)) can then be calculated as Equation 9 and Equation 10.

The requirements for the output voltages of amplifiers A1 and A2 (Equation 5) can now be translated into requirements for the input common-mode voltage range using Equation 9 and Equation 10, which are given in Equation 11 and Equation 12.

To calculate the minimum and maximum common-mode voltage limits, the maximum differential input voltage (V_{IN (MAX)}) that occurs in the application must be used. V_{IN (MAX)} can be less than the maximum possible full-scale value.

9.3.2.2 PGA Common-Mode Voltage Calculation Example

The following paragraphs explain how to apply Equation 11 and Equation 12 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference, V_REF = 2.5 V. The maximum possible differential input voltage V_IN = (V_(AINP) – V_(AINN)) that can be applied is then limited to the full-scale range of FSR = ±2.5 V / 16 = ±0.156 V. Consequently, Equation 11 and Equation 12 yield an allowed V_CM range of 1.35 V ≤ V_CM ≤ 1.95 V.

If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-scale range but is limited to V_{IN (MAX)} = ±0.1 V, for example, then this reduced input signal amplitude relaxes the V_CM restriction to 0.9 V ≤ V_CM ≤ 2.4 V.

In the case of a fully-differential sensor signal, each input (AIN_P, AIN_N) can swing up to ±50 mV around the common-mode voltage (V_(AINP) + V_(AINN)) / 2, which must remain between the limits of 0.9 V and 2.4 V. The output of a symmetrical wheatstone bridge is an example of a fully-differential signal. Figure 54 shows a situation where the common-mode voltage of the input signal is at the lowest limit. V_(OUTN) is exactly at 0.1 V in this case. Any further decrease in common-mode voltage (V_CM) or increase in differential input voltage (V_IN) drives V_(OUTN) below 0.1 V and saturates amplifier A2.

Figure 54. Example where V_CM is at Lowest Limit

In contrast, the signal of an RTD is of a pseudo-differential nature (if implemented as shown in one of the application example sections, 3-Wire RTD Measurement), where the negative input is held at a constant voltage other than 0 V and only the voltage on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this example must be biased at a voltage from 0.85 V to 2.35 V. The positive input can then swing up to V_{IN (MAX)} = 100 mV above the negative input. In this case, the common-mode voltage changes at the same time the voltage on the positive input changes. That is, while the input signal swings between 0 V ≤ V_IN ≤ V_{IN (MAX)}, the common-mode voltage swings between V_(AINN) ≤ V_CM ≤ V_(AINN) + ½ V_{IN (MAX)}. Satisfying the common-mode voltage requirements for the maximum input voltage V_{IN (MAX)} ensures the requirements are met throughout the entire signal range.

Figure 55 and Figure 56 show examples of both fully-differential and pseudo-differential signals, respectively.

Figure 55. Fully-Differential Input Signal

Figure 56. Pseudo-Differential Input Signal

9.3.2.3 Analog Input Impedance

The device inputs are buffered through a high-input impedance PGA before they reach the ΔΣ modulator. For the majority of applications, the input current is minimal and can be neglected. However, because the PGA is chopper-stabilized for noise and offset performance, the input impedance is best described as a small absolute input current. The absolute input current for selected channels is approximately proportional to the selected modulator clock. Table 8 shows the typical values for these currents with a differential voltage coefficient and the corresponding input impedances over data rate.

Table 9. Modulator Clock Frequency for Different Data Rates

Table 10. Digital Filter Specifications⁽¹⁾

Table 11. Internal Reference Settling Time

Table 12. Bias Voltage Settling Time

9.3.12.1 Power-Supply Monitor

The system monitor can measure the analog or digital power supply. When measuring the power supply (V_SP), the resulting conversion is approximately 1/4 of the actual power supply voltage, as shown in Equation 15.

9.3.12.2 External Voltage Reference Monitor

The ADC can measure the external voltage reference. In this configuration, the monitored external voltage reference (V_REX) is connected to the analog input. The result (conversion code) is approximately 1/4 of the actual reference voltage, as shown in Equation 16.

9.3.12.3 Ambient Temperature Monitor

On-chip diodes provide temperature-sensing capability. When selecting the temperature monitor function, the anodes of two diodes are connected to the ADC. Typically, the difference in diode voltage is 118 mV at
T_A = 25°C with a temperature coefficient of 405 μV/°C.

Table 13. Start Pin Conversion Times for Figure 70⁽¹⁾

9.4.4.1 Settling Time for Channel Multiplexing

The device is a true single-cycle settling ΔΣ converter. The first data available after the start of a conversion are fully settled and valid for use, provided that the input signal has settled to its final result. The time required to settle is roughly equal to the inverse of the data rate. The exact time depends on the specific data rate and the operation that resulted in the start of a conversion; see Table 14 for specific values.

9.4.4.2 Channel Cycling and Overload Recovery

When cycling through channels, take care when configuring the device to ensure that settling occurs within one cycle. For setups that cycle through MUX channels, but do not change PGA and data rate settings, changing the MUX0 register is sufficient. However, when changing PGA and data rate settings, ensure that an overloaded condition cannot occur during the transmission. When configuration register data are transferred to the device, new settings become active at the end of each register byte sent. Therefore, a brief overload condition can occur during the transmission of configuration data after the completion of the MUX0 byte and before completion of the SYS0 byte. This temporary overload can result in intermittent incorrect readings. To ensure that an overload does not occur, it may be necessary to split the communication into two separate communications allowing the change of the SYS0 register before the change of the MUX0 register.

In the event of an overloaded state, take care to ensure single-cycle settling into the next cycle. Because the device implements a chopper-stabilized PGA, changing data rates during an overload state can cause the chopper to become unstable. This instability results in slow settling time. To prevent this slow settling, always change the PGA setting or MUX setting to a non-overloaded state before changing the data rate.

9.4.4.3 Single-Cycle Settling

The ADS1246, ADS1247, and ADS1248 are capable of single-cycle settling across all gains and data rates. However, to achieve single-cycle settling at 2 kSPS, special care must be taken with respect to the interface using WREG to change a configuration register. When operating at 2 kSPS, the SCLK period must not exceed 520 ns, and the time between the beginning of writing a register byte data and the beginning of a subsequent register byte data must not exceed 4.2 µs. Additionally, when performing multiple individual write commands to the first four registers, wait at least 64 system clocks before initiating another write command.

9.4.4.4 Digital Filter Reset Operation

Apart from the RESET command and the RESET pin, the digital filter is reset automatically when either a write operation to the MUX0, VBIAS, MUX1, or SYS0 registers is performed, when a SYNC command is issued, or the START pin is taken high.

The filter is reset four system clocks (t_CLK) after the falling edge of the seventh SCLK of the SYNC command. Similarly, if any write operation takes place in the MUX0 register, regardless of whether the register value changed or not, the filter is reset after the completion of the MUX0 write.

If any write activity takes place in the VBIAS, MUX1, or SYS0 registers, regardless of whether the register value changed or not, the filter is reset. The reset pulse lasts for 32 modulator clocks after the completion of the write operation. If there are multiple write operations, the resulting reset pulse may be viewed as the ANDed result of the different active low pulses created individually by each action.

Table 14 shows the conversion time after a filter reset. Note that this time depends on the operation initiating the reset. Also, the first conversion after a filter reset has a slightly different time than the second and subsequent conversions.

9.4.5.1 Offset Calibration Register: OFC[2:0]

The offset calibration register is a 24-bit word, composed of three 8-bit registers. The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from the conversion data. A register value of 000000h provides no offset correction. Note that while the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 15), avoid overloading the analog inputs.

9.4.5.2 Full-Scale Calibration Register: FSC[2:0]

The full-scale or gain calibration register is a 24-bit word composed of three 8-bit registers. The full-scale calibration value is 24-bit, straight binary, normalized to 1.0 at code 400000h. Table 16 summarizes the scaling of the full-scale register. Note that while the full-scale calibration register can correct gain errors > 1 (with gain scaling < 1), make sure to avoid overloading the analog inputs. The default or reset value of FSC depends on the PGA gain setting. A different factory-trimmed FSC reset value is stored for each PGA gain setting which provides gain accuracy over all the device input ranges.

9.4.5.3 Calibration Commands

The device provides commands for three types of calibration: system gain calibration, system offset calibration and self offset calibration. Where absolute accuracy is needed, TI recommends performing a calibration after power up, a change in temperature, a change of gain, and in some cases a change in channel. At the completion of calibration, the DRDY signal goes low indicating the calibration has completed. The first data after calibration are always valid. If the START pin is taken low or a SLEEP command is issued after any calibration command, the device powers down after completing calibration.

After a calibration has started, allow the calibration to complete before issuing any other commands (other than the SLEEP command). Issuing commands during a calibration can result in corrupted data. If this occurs, either resend the calibration command that was aborted or issue a device reset.

9.4.5.4 Calibration Timing

When calibration is initiated, the device performs 16 consecutive data conversions and averages the results to calculate the calibration value. This provides a more accurate calibration value. The time required for calibration is shown in Table 17 and can be calculated using Equation 19:

Equation 19.

where

9.5.1.1 Chip Select (CS)

The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the entire SPI communication period. When CS is high, the DOUT/DRDY pin enters a high-impedance state. Therefore, reading and writing to the serial interface are ignored and the serial interface is reset. DRDY pin operation is independent of CS. DRDY will still indicate that a new conversion has completed and is forced high as a response to SCLK, even if CS is high.

Taking CS high deactivates only the SPI communication with the device. Data conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low.

9.5.1.2 Serial Clock (SCLK)

SCLK provides the clock for serial communication. SCLK is a Schmitt-trigger input, but TI recommends keeping SCLK as free from noise as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and shifted out of DOUT on the rising edge of SCLK.

9.5.1.3 Data Input (DIN)

DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the falling edge of SCLK.

The communication of this device is full-duplex in nature. The device monitors commands shifted in even when data are being shifted out. Data that are present in the output shift register are shifted out when sending in a command. Therefore, make sure that whatever is being sent on the DIN pin is valid when shifting out data. When no command is to be sent to the device when reading out data, send the NOP command on DIN.

9.5.1.4 Data Ready (DRDY)

The DRDY pin goes low to indicate a new conversion is complete, and the conversion result is stored in the conversion result buffer. SCLK must be held low for t_DTS after the DRDY low transition (see Figure 2) so that the conversion result is loaded into both the result buffer and the output shift register. Therefore, issue no commands during this time frame if the conversion result is to be read out later. This constraint applies only when CS is asserted and the device is in RDATAC mode. When CS is not asserted, SPI communication with other devices on the SPI bus does not affect loading of the conversion result. After the DRDY pin goes low, it is forced high on the first falling edge of SCLK (so that the DRDY pin can be polled for 0 instead of waiting for a falling edge). If the DRDY pin is not taken high by clocking in SCLKs after it falls low, a short high pulse for a duration of t_PWH indicates new data are ready.

9.5.1.5 Data Output and Data Ready (DOUT/DRDY)

The DOUT/DRDY pin has two modes: data out (DOUT) only, or DOUT combined with data ready (DRDY). The DRDY MODE bit determines the function of this pin and can be found in the ID register in the ADS1246 and the IDAC0 register in the ADS1247 and ADS1248. In either mode, the DOUT/DRDY pin goes to a high-impedance state when CS is taken high.

When the DRDY MODE bit is set to 0, this pin functions as DOUT only. Data are clocked out on the rising edge of SCLK, MSB first (as shown in Figure 73).

When the DRDY MODE bit is set to 1, this pin functions as both DOUT and DRDY. Data are shifted out as with DOUT, but the pin adds the DRDY function. Note that this mode will not be operational when the device is in stop read data continuous mode when the SDATAC command is given.

The DRDY MODE bit modifies only the DOUT/DRDY pin functionality. The DRDY pin functionality remains unaffected.

1.

NOINDENT:

CS tied low.

Figure 73. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)

When the DRDY MODE bit is enabled and a new conversion is complete, DOUT/DRDY goes low if it is high. If it is already low, then DOUT/DRDY goes high and then goes low (as shown in Figure 74). Similar to the DRDY pin, a falling edge on the DOUT/DRDY pin signals that a new conversion result is ready. After DOUT/DRDY goes low, the data can be clocked out by providing 24 SCLKs if the device is in read data continuous mode. In order to force DOUT/DRDY high (so that DOUT/DRDY can be polled for a 0 instead of waiting for a falling edge), a no operation command (NOP) or any other command that does not load the data output register can be sent after reading out the data. Because SCLKs can only be sent in multiples of eight, a NOP can be sent to force DOUT/DRDY high if no other command is pending. The DOUT/DRDY pin goes high after the first rising edge of SCLK after reading the conversion result completely (as shown in Figure 75). The same condition also applies after an RREG command. After all the register bits have been read out, the first rising edge of SCLK forces DOUT/DRDY high. Figure 76 shows an example where sending an extra NOP command after reading out a register with an RREG command forces the DOUT/DRDY pin high.

1.

NOINDENT:

CS tied low.

Figure 74. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)

1.

NOINDENT:

DRDY MODE bit enabled, CS tied low.

Figure 75. DOUT/DRDY Forced High after Retrieving the Conversion Result

1.

NOINDENT:

DRDY MODE bit enabled, CS tied low.

Figure 76. DOUT/DRDY Forced High after Reading Register Data

9.5.1.6 SPI Reset

SPI communication is reset in several ways. To reset the serial interface (without resetting the registers or the digital filter), the CS pin can be pulled high. Taking the RESET pin low resets the serial interface along with all the other digital functions. It will also return all registers to their default values and start a new conversion.

In systems where CS is tied low permanently, register writes must always be fully completed in 8-bit increments. If a glitch on SCLK disrupts SPI communications, commands will not be recognized by the device. The device implements a timeout function for all listed commands in the event that data are corrupted and the CS pin is permanently tied low. The SPI timeout will reset the interface if idle for 64 conversion cycles.

9.5.1.7 SPI Communication During Power-Down Mode

When the START pin is low or the device is in power-down mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued. The RDATA command can be used to repeatedly read the last conversion result during power-down mode. Other commands do not function because the internal clock is shut down to save power during power-down mode.

Table 18. Ideal Output Code vs Input Signal

Table 19. SPI Commands

9.5.3.1 WAKEUP (0000 000x)

Use the WAKEUP command to power up the device after a SLEEP command. After execution of the WAKEUP command, the device powers up on the falling edge of the eighth SCLK.

9.5.3.2 SLEEP (0000 001x)

The SLEEP command places the device into power-down mode. When the SLEEP command is issued, the device completes the current conversion and then goes into power-down mode. Note that this command does not automatically power down the internal voltage reference; see the VREFCON bits in MUX1 for each device for further details.

To exit power-down mode, issue the WAKEUP command. Single conversions can be performed by issuing a WAKEUP command followed by a SLEEP command.

Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device, as shown in Figure 78.

Figure 78. SLEEP and WAKEUP Commands Operation

9.5.3.3 SYNC (0000 010x)

The SYNC command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices simultaneously.

Figure 79. SYNC Command Operation

9.5.3.4 RESET (0000 011X)

The RESET command restores the registers to the respective default values. This command also resets the digital filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET command does not reset the serial interface. If the RESET command is issued when the serial interface is out of synchonization due to a glitch on SCLK, the device does not reset. The CS pin can be used to reset the serial interface first, and then a RESET command can be issued to reset the device. The RESET command holds the registers and the decimation filter in a reset state for 0.6 ms when the system clock frequency is 4.096 MHz, similar to the hardware reset. Therefore, SPI communication can be only be started 0.6 ms after the RESET command is issued, as shown in Figure 80.

Figure 80. SPI Communication after an SPI Reset

9.5.3.5 RDATA (0001 001x)

The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result is read out by sending 24 SCLKs, as shown in Figure 81. This command also works in RDATAC mode.

Figure 81. Read Data Once

When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight bits of the conversion result are being shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the serial interface, as shown in Figure 82.

Figure 82. Using RDATA in Full-Duplex Mode

9.5.3.6 RDATAC (0001 010x)

The RDATAC command enables read data continuous mode. This is the default mode after a power up or reset. In read data continuous mode, new conversion results are automatically loaded onto DOUT. The conversion result can be received from the device after the DRDY signal goes low by sending 24 SCLKs. It is not necessary to read back all the bits, as long as the number of bits read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the command takes effect on the next DRDY.

Be sure to complete data retrieval (conversion result or register read-back) before DRDY returns low, or the resulting data will be corrupt. Successful register read operations in RDATAC mode require the knowledge of when the next DRDY falling edge occurs.

Figure 83. Read Data Continuously

9.5.3.7 SDATAC (0001 011x)

The SDATAC command terminates read data continuous mode. In stop read data continuous mode, the conversion result is not automatically loaded onto DOUT when DRDY goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. Use the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.

If DRDY is not actively monitored for data conversions, the stop read data continuous mode is the preferred method of reading data. In this mode, a read of ADC data is not interrupted by the completion of a new ADC conversion.

9.5.3.8 RREG (0010 rrrr, 0000 nnnn)

The RREG command outputs the data from up to 15 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the value of the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. The two byte command structure for RREG is listed below.

• First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.
• Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1.
• Byte(s): data read from the registers are clocked out with NOPs.

It is not possible to use the full-duplex nature of the serial interface when reading out the register data. For example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in Figure 84. Any command sent during the readout of the register data is ignored. Thus, TI recommends sending NOPs through DIN when reading out the register data.

Figure 84. Read from Register

9.5.3.9 WREG (0100 rrrr, 0000 nnnn)

The WREG command writes to the registers, starting with the register specified as part of the instruction. The number of registers that are written is one plus the value of the second byte. The command structure for WREG is listed below.

• First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written.
• Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1.
• Byte(s): data to be written to the registers.

Figure 85. Write to Register

9.5.3.10 SYSOCAL (0110 0000)

The SYSOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be externally shorted to a voltage within the input common mode range. The inputs should be near the mid-supply voltage of (AVDD + AVSS) / 2. The OFC register is updated when the command completes. Timing for the calibration commands can be found in Figure 86.

Figure 86. Calibration Command

9.5.3.11 SYSGCAL (0110 0001)

The SYSGCAL command initiates the system gain calibration. For a system gain calibration, the input should be set to full-scale. The FSC register is updated after this operation. Timing for the calibration commands can be found in Figure 86.

9.5.3.12 SELFOCAL (0110 0010)

The SELFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply and performs the calibration. The OFC register is updated after this operation. Timing for the calibration commands can be found in Figure 86.

9.5.3.13 NOP (1111 1111)

This is a no-operation command. This is used to clock out data without clocking in a command.

9.5.3.14 Restricted Command (1111 0001)

This is a restricted command. This command should never be issued to the device.

Table 20. ADS1246 Register Map

9.6.2.1 BCS—Burn-out Current Source Register (offset = 00h) [reset = 01h]

These bits control the sensor burn-out detect current source.

9.6.2.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]

This register enables a bias voltage on the analog inputs.

9.6.2.3 MUX—Multiplexer Control Register (offset = 02h) [reset = x0h]

Table 24 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

9.6.2.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h]

9.6.2.5 OFC—Offset Calibration Coefficient Registers (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]

These bits make up the offset calibration coefficient register of the ADS1246.

9.6.2.6 FSC—Full-Scale Calibration Coefficient Registers (offset = 07h, 08h, 09h) [reset = PGA dependent]

These bits make up the full-scale calibration coefficient register. The reset value for FSC is factory-trimmed for each PGA setting. The factory-trimmed FSC reset value is automatically loaded whenever the PGA setting is changed.

9.6.2.7 ID—ID Register (offset = 0Ah) [reset = x0h]

Table 28. ID Register Field Descriptions

Table 29. ADS1247 and ADS1248 Register Map

9.6.4.1 MUX0—Multiplexer Control Register 0 (offset = 00h) [reset = 01h]

This register allows any combination of differential inputs to be selected on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.

9.6.4.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]

9.6.4.3 MUX1—Multiplexer Control Register 1 (offset = 02h) [reset = x0h]

Table 34 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

9.6.4.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h]

9.6.4.5 OFC—Offset Calibration Coefficient Register (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]

These bits make up the offset calibration coefficient register of the ADS1247 and ADS1248.

9.6.4.6 FSC—Full-Scale Calibration Coefficient Register (offset = 07h, 08h, 09h) [reset = PGA dependent]

These bits make up the full-scale calibration coefficient register. The reset value for FSC is factory-trimmed for each PGA setting. The factory-trimmed FSC reset value is automatically loaded whenever the PGA setting is changed.

9.6.4.7 IDAC0—IDAC Control Register 0 (offset = 0Ah) [reset = x0h]

9.6.4.8 IDAC1—IDAC Control Register 1 (offset = 0Bh) [reset = FFh]

The two IDACs on the ADS1248 can be routed to either the IEXC1 and IEXC2 output pins or directly to the analog inputs.

9.6.4.9 GPIOCFG—GPIO Configuration Register (offset = 0Ch) [reset = 00h]

9.6.4.10 GPIODIR—GPIO Direction Register (offset = 0Dh) [reset = 00h]

9.6.4.11 GPIODAT—GPIO Data Register (offset = 0Eh) [reset = 00h]