SBAS442D august   2008  – august 2023 DAC5311 , DAC6311 , DAC7311

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements
    7. 7.7  Timing Diagrams
    8. 7.8  Typical Characteristics: AVDD = 5 V
    9. 7.9  Typical Characteristics: AVDD = 3.6 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Input Shift Register
        2. 8.5.1.2 SYNC Interrupt
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Microprocessor Interfacing
        1. 9.1.1.1 DACx311 to 8051 Interface
        2. 9.1.1.2 DACx311 to Microwire Interface
        3. 9.1.1.3 DACx311 to 68HC11 Interface
    2. 9.2 Typical Applications
      1. 9.2.1 Loop Powered Transmitter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Using the REF5050 as a Power Supply for the DACx311
      3. 9.2.3 Bipolar Operation Using the DACx311
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

9.2.1.2 Detailed Design Procedure

Amplifier U1 uses negative feedback to make sure that the potentials at the inverting (V–) and noninverting (V+) input terminals are equal. In this configuration, V– is directly tied to the local GND; therefore, the potential at the noninverting input terminal is driven to local ground. Thus, the voltage difference across R2 is the DAC output voltage (VOUT), and the voltage difference across R5 is the regulator voltage (VREG). These voltage differences cause currents to flow through R2 and R5, as illustrated in Figure 9-5.

GUID-4B829442-02C4-4B86-908D-FF823255BB54-low.gif Figure 9-5 Voltage to Current Conversion

The currents from R2 and R5 sum into i1 (defined in Equation 2), and i1 flows through R3.

Equation 2. GUID-B2E4440F-BE0B-4C32-BF10-1193BF67B703-low.gif

Amplifier U2 drives the base of Q1, the NPN bipolar junction transistor (BJT), to allow current to flow through R4 so that the voltage drops across R3 and R4 remain equal. This design keeps the inverting and noninverting terminals at the same potential. A small part of the current through R4 is sourced by the quiescent current of all of the components used in the transmitter design (regulator, amplifier, and DAC). The voltage drops across R3 and R4 are equal; therefore, different-sized resistors cause different current flow through each resistor. Use these different-sized resistors to apply gain to the current flow through R4 by controlling the ratio of resistor R3 to R4, as shown in Equation 3:

Equation 3. GUID-080CDE90-5C25-4C60-B511-23385CB7EA04-low.gif

The current gain in the circuit helps allow a majority of the output current to come directly from the loop through Q1 instead of from the voltage-to-current converter. This current gain, in addition to the low-power components, keeps the current consumption of the voltage-to-current converter low. Currents i1 and i2 sum to form output current iout, as shown in Equation 4:

Equation 4. GUID-CCC65C23-D57F-41A7-A9D8-E6F871CE8BDE-low.gif

The complete transfer function, arranged as a function of input code, is shown in Equation 5. The remaining sections divide this circuit into blocks for simplified discussion.

Equation 5. GUID-441E33C1-7FE2-4BDC-9EAF-59F4536BC884-low.gif

Resistor R6 is included to reduce the gain of transistor Q1, and therefore, reduce the closed-loop gain of the voltage-to-current converter for a stable design. Size resistors R2, R3, R4, and R5 based on the full-scale range of the DAC, regulator voltage, and the desired current output range of the design.