SBAS502C December   2011  – April 2020 ADS1291 , ADS1292 , ADS1292R

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Block Diagram
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EMI Filter
      2. 8.3.2  Input Multiplexer
        1. 8.3.2.1 Device Noise Measurements
        2. 8.3.2.2 Test Signals (TestP and TestN)
        3. 8.3.2.3 Auxiliary Differential Input (RESP_MODN/IN3N, RESP_MODN/IN3P)
        4. 8.3.2.4 Temperature Sensor (TEMPP, TEMPN)
        5. 8.3.2.5 Supply Measurements (MVDDP, MVDDN)
        6. 8.3.2.6 Lead-Off Excitation Signals (LoffP, LoffN)
        7. 8.3.2.7 Auxiliary Single-Ended Input
      3. 8.3.3  Analog Input
      4. 8.3.4  PGA Settings and Input Range
        1. 8.3.4.1 Input Common-Mode Range
        2. 8.3.4.2 Input Differential Dynamic Range
        3. 8.3.4.3 ADC ΔΣ Modulator
      5. 8.3.5  Digital Decimation Filter
        1. 8.3.5.1 Sinc Filter Stage (sinx / x)
      6. 8.3.6  Reference
      7. 8.3.7  Clock
      8. 8.3.8  Data Format
      9. 8.3.9  Multiple Device Configuration
        1. 8.3.9.1 Standard Mode
      10. 8.3.10 ECG-Specific Functions
        1. 8.3.10.1 Input Multiplexer (Rerouting the Right Leg Drive Signal)
          1. 8.3.10.1.1 Input Multiplexer (Measuring the Right Leg Drive Signal)
        2. 8.3.10.2 Lead-Off Detection
          1. 8.3.10.2.1 DC Lead-Off
          2. 8.3.10.2.2 AC Lead-Off
          3. 8.3.10.2.3 RLD Lead-Off
          4. 8.3.10.2.4 Right Leg Drive (RLD DC Bias Circuit)
            1. 8.3.10.2.4.1 RLD Configuration With Multiple Devices
        3. 8.3.10.3 PACE Detect
        4. 8.3.10.4 Respiration
          1. 8.3.10.4.1 Internal Respiration Circuitry With Internal Clock (ADS1292R)
          2. 8.3.10.4.2 Internal Respiration Circuitry With External Clock (ADS1292R)
      11. 8.3.11 Setting the Device for Basic Data Capture
        1. 8.3.11.1 Lead-Off
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Clock (SCLK)
        3. 8.5.1.3  Data Input (DIN)
        4. 8.5.1.4  Data Output (DOUT)
        5. 8.5.1.5  Data Retrieval
        6. 8.5.1.6  Data Ready (DRDY)
        7. 8.5.1.7  GPIO
        8. 8.5.1.8  Power-Down and Reset (PWDN/RESET)
        9. 8.5.1.9  START
        10. 8.5.1.10 Settling Time
        11. 8.5.1.11 Continuous Mode
        12. 8.5.1.12 Single-Shot Mode
      2. 8.5.2 SPI Command Definitions
        1. 8.5.2.1  WAKEUP: Exit STANDBY Mode
        2. 8.5.2.2  STANDBY: Enter STANDBY Mode
        3. 8.5.2.3  RESET: Reset Registers to Default Values
        4. 8.5.2.4  START: Start Conversions
        5. 8.5.2.5  STOP: Stop Conversions
        6. 8.5.2.6  OFFSETCAL: Channel Offset Calibration
        7. 8.5.2.7  RDATAC: Read Data Continuous
        8. 8.5.2.8  SDATAC: Stop Read Data Continuous
        9. 8.5.2.9  RDATA: Read Data
        10. 8.5.2.10 Sending Multi-Byte Commands
        11. 8.5.2.11 RREG: Read From Register
        12. 8.5.2.12 WREG: Write to Register
    6. 8.6 Register Maps
      1. 8.6.1 User Register Description
        1. 8.6.1.1  ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h)
          1. Table 17. ID: ID Control Register (Factory-Programmed, Read-Only) Field Descriptions
        2. 8.6.1.2  CONFIG1: Configuration Register 1 (address = 01h)
          1. Table 18. CONFIG1: Configuration Register 1 Field Descriptions
        3. 8.6.1.3  CONFIG2: Configuration Register 2 (address = 02h)
          1. Table 19. CONFIG2: Configuration Register 2 Field Descriptions
        4. 8.6.1.4  LOFF: Lead-Off Control Register (address = 03h)
          1. Table 20. LOFF: Lead-Off Control Register Field Descriptions
        5. 8.6.1.5  CH1SET: Channel 1 Settings (address = 04h)
          1. Table 21. CH1SET: Channel 1 Settings Field Descriptions
        6. 8.6.1.6  CH2SET: Channel 2 Settings (address = 05h)
          1. Table 22. CH2SET: Channel 2 Settings Field Descriptions
        7. 8.6.1.7  RLD_SENS: Right Leg Drive Sense Selection (address = 06h)
          1. Table 23. RLD_SENS: Right Leg Drive Sense Selection Field Descriptions
        8. 8.6.1.8  LOFF_SENS: Lead-Off Sense Selection (address = 07h)
          1. Table 24. LOFF_SENS: Lead-Off Sense Selection Field Descriptions
        9. 8.6.1.9  LOFF_STAT: Lead-Off Status (address = 08h)
          1. Table 25. LOFF_STAT: Lead-Off Status Field Descriptions
        10. 8.6.1.10 RESP1: Respiration Control Register 1 (address = 09h)
          1. Table 26. RESP1: Respiration Control Register 1 Field Descriptions
        11. 8.6.1.11 RESP2: Respiration Control Register 2 (address = 0Ah)
          1. Table 27. RESP2: Respiration Control Register 2 Field Descriptions
        12. 8.6.1.12 GPIO: General-Purpose I/O Register (address = 0Bh)
          1. Table 28. GPIO: General-Purpose I/O Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout
        1. 11.1.1.1 Power Supplies and Grounding
          1. 11.1.1.1.1 Connecting the Device to Unipolar (+3 V or +1.8 V) Supplies
          2. 11.1.1.1.2 Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies
        2. 11.1.1.2 Shielding Analog Signal Paths
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

minimum and maximum specifications apply from –40°C to +85°C; typical specifications are at +25°C; all specifications are at DVDD = 1.8 V, AVDD – AVSS = 3 V(3), VREF = 2.42 V, external fCLK = 512 kHz, data rate = 500 SPS, CFILTER = 4.7 nF(4), and gain = 6 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale differential input voltage
(AINP – AINN)		 ±VREF / gain V
Input common-mode range See the Input Common-Mode Range subsection of the PGA Settings and Input Range section
Input capacitance 20 pF
Input bias current (PGA chop = 8 kHz) TA = +25°C, input = 1.5 V ±200 pA
TA = –40°C to +85°C, input = 1.5 V ±1 nA
Chop rates other than 8 kHz See Pace Detect section
DC input impedance No pull-up or pull-down current source 1000 MΩ
Current source lead-off detection (nA),
AVSS + 0.3 V < AIN < AVDD – 0.3 V		 500 MΩ
Current source lead-off detection (µA),
AVSS + 0.6 V < AIN < AVDD – 0.6 V		 100 MΩ
PGA PERFORMANCE
Gain settings 1, 2, 3, 4, 6, 8, 12
Bandwidth With a 4.7-nF capacitor on PGA output
(see PGA Settings and Input Range section for details)		 8.5 kHz
ADC PERFORMANCE
Resolution 24 Bits
Data rate fCLK = 512 kHz 125 8000 SPS
CHANNEL PERFORMANCE (DC Performance)
Input-referred noise Gain = 6(1), 10 seconds of data 8 μVPP
Gain = 6, 256 points, 0.5 seconds of data 8 11 μVPP
Gain settings other than 6,
data rates other than 500 SPS		 See Noise Measurements section
Integral nonlinearity Full-scale with gain = 6, best fit 2 ppm
Offset error ±100 μV
Offset error drift 2 μV/°C
Offset error with calibration 15 μV
Gain error Excluding voltage reference error ±0.1 ±0.2 % of FS
Gain drift Excluding voltage reference drift 2 ppm/°C
Gain match between channels 0.2 % of FS
CHANNEL PERFORMANCE (AC performance)
CMRR Common-mode rejection ratio fCM = 50 Hz and 60 Hz(2) 105 120 dB
PSRR Power-supply rejection ratio fPS = 50 Hz and 60 Hz 90 dB
Crosstalk fIN = 50 Hz and 60 Hz –120 dB
SNR Signal-to-noise ratio fIN = 10 Hz input, gain = 6 107 dB
THD Total harmonic distortion 10 Hz, –0.5 dBFs, CFILTER = 4.7nF –104 dB
100 Hz, –0.5 dBFs, CFILTER = 4.7nF –95 dB
ADS1292R channel 1, 10 Hz, –0.5 dBFS, CFILTER = 47 nF –82 dB
DIGITAL FILTER
–3-dB bandwidth 0.262 fDR Hz
Digital filter settling Full setting 4 Conversions
RIGHT LEG DRIVE (RLD) AMPLIFIER
RLD integrated noise BW = 150 Hz 1.4 μVRMS
GBP Gain bandwidth product 50 kΩ || 10 pF load, gain = 1 100 kHz
SR Slew rate 50 kΩ || 10 pF load, gain = 1 0.07 V/μs
THD Total harmonic distortion fIN = 100 Hz, gain = 1 –85 dB
CMIR Common-mode input range AVSS + 0.3 AVDD – 0.3 V
Common-mode resistor matching Internal 200-kΩ resistor matching 0.1 %
ISC Short-circuit current 1.1 mA
Quiescent power consumption 5 μA
LEAD-OFF DETECT
Frequency See Register Map section for settings 0, fDR / 4 kHz
Current ILEAD_OFF [1:0] = 00 6 nA
ILEAD_OFF [1:0] = 01 22 nA
ILEAD_OFF [1:0] = 10 6 μA
ILEAD_OFF [1:0] = 11 22 μA
Current accuracy ±10 %
Comparator threshold accuracy ±10 mV
RESPIRATION (ADS1292R)
Frequency Internal source 32, 64 kHz
External source 32 64 kHz
Phase shift See Register Map section for settings 0 112.5 168.75 Degrees
Impedance range IRESP = 30 µA 2000 10,000 Ω
Impedance measurement noise 0.05-Hz to 2-Hz brick wall filter, 32-kHz modulation clock, phase = 112.5,
using IRESP = 30 µA with 2-kΩ baseline load, gain = 4 		40 mΩPP
Maximum modulator current Using Internal reference 100 μA
EXTERNAL REFERENCE
Reference input voltage 3-V supply VREF = (VREFP – VREFN) 2 2.5 VDD – 0.3 V
5-V supply VREF = (VREFP – VREFN) 2 4 VDD – 0.3 V
VREFN Negative input AVSS V
VREFP Positive input AVSS + 2.5 V
Input impedance 120 kΩ
INTERNAL REFERENCE
Output voltage Register bit CONFIG2.VREF_4V = 0 2.42 V
Register bit CONFIG2.VREF_4V = 1 4.033 V
Output current drive Available for external use 100 µA
VREF accuracy ±0.5 %
Internal reference drift –40°C ≤ TA ≤ +85°C 45 ppm/°C
Start-up time Settled to 0.2% with 10-µF capacitor on VREFP pin 100 ms
Quiescent current consumption 20 µA
SYSTEM MONITORS
Analog supply reading error 1 %
Digital supply reading error 1 %
Device wake up From power-supply ramp after power-on reset (POR) to DRDY low 32 ms
From power-down mode to DRDY low 10 ms
From STANDBY mode to DRDY low 10 ms
VCAP1 settling time 1% accuracy 0.5 s
Temperature sensor reading Voltage TA = +25°C 145 mV
Coefficient 490 μV/°C
TEST SIGNAL
Signal frequency See Register Map section for settings At dc and 1 Hz Hz
Signal voltage See Register Map section for settings ±1 mV
Accuracy ±2 %
CLOCK
Internal oscillator clock frequency Nominal frequency 512 kHz
Internal clock accuracy TA = +25°C ±0.5 %
–40°C ≤ TA ≤ +85°C ±1.5 %
Internal oscillator start-up time 32 μs
Internal oscillator power consumption 30 μW
External clock input frequency CLKSEL pin = 0, CLK_DIV = 0 485 512 562.5 kHz
CLKSEL pin = 0, CLK_DIV = 1 1.94 2.048 2.25 MHz
DIGITAL INPUT/OUTPUT
VIH Logic level DVDD = 1.8 V to 3.6 V 0.8 DVDD DVDD + 0.1 V
VIL DVDD = 1.8 V to 3.6 V –0.1 0.2 DVDD V
VIH DVDD = 1.7 V to 1.8 V DVDD – 0.2 V
VIL DVDD = 1.7 V to 1.8 V 0.2 V
VOH DVDD = 1.7 V to 3.6 V IOH = –500 μA 0.9 DVDD V
VOL DVDD = 1.7 V to 3.6 V IOL = +500 μA 0.1 DVDD V
IIN Input current 0 V < VDigitalInput < DVDD –10 +10 μA
POWER-SUPPLY REQUIREMENTS
AVDD Analog supply AVDD – AVSS 2.7 3 5.25 V
DVDD Digital supply DVDD – DGND 1.7 1.8 3.6 V
AVDD – DVDD –2.1 3.6 V
SUPPLY CURRENT (RLD Amplifier Turned Off)
IAVDD ADS1292 and ADS1292R AVDD – AVSS = 3 V 205 μA
AVDD – AVSS = 5 V 250 μA
IDVDD ADS1292 and ADS1292R DVDD = 3.3 V 75 μA
DVDD = 1.8 V 32 μA
POWER DISSIPATION (Analog Supply = 3 V, RLD Amplifier Turned Off)
Quiescent power dissipation ADS1292 and ADS1292R Normal mode 670 740 µW
Standby mode 160 µW
ADS1291 Normal mode 450 495 µW
Standby mode 160 µW
Quiescent power dissipation, per channel ADS1292R Normal mode 335 µW
ADS1292 Normal mode 335 µW
ADS1291 Normal mode 450 µW
POWER DISSIPATION (Analog Supply = 5 V, RLD Amplifier Turned Off)
Quiescent power dissipation ADS1292 and ADS1292R Normal mode 1300 µW
Standby mode 340 µW
ADS1291 Normal mode 950 µW
Standby mode 340 µW
Quiescent power dissipation, per channel ADS1292R Normal mode 670 µW
ADS1292 Normal mode 670 µW
ADS1291 Normal mode 860 µW
POWER DISSIPATION IN POWER-DOWN MODE
Analog supply = 3 V DVDD = 1.8 V 1 µW
DVDD = 3.3 V 4 µW
Analog supply = 5 V DVDD = 1.8 V 5 µW
DVDD = 3.3 V 10 µW
TEMPERATURE
Specified temperature range –40 +85 °C
Operating temperature range –40 +85 °C
Storage temperature range –60 +150 °C
(1) Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with input shorted (without electrode resistance) over a 10-second interval.
(2) CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the minimum of the two channels.
(3) Performance is applicable for 5-V operation as well. Production testing for limits is performed at 3 V.
(4) CFILTER is the capacitor accross the PGA outputs; see the PGA Settings and Input Range section for details.