The ADS8555 device contains six low-power, 16-bit, successive approximation register (SAR)-based analog-to-digital converters (ADCs) with true bipolar inputs. Each channel contains a sample-and-hold circuit that allows simultaneous high-speed multi-channel signal acquisition.
The ADS8555 device supports data rates of up to 630 kSPS in parallel interface mode or up to 450 kSPS if the serial interface is used. The bus width of the parallel interface can be set to eight or 16 bits. In serial mode, up to three output channels can be activated.
The ADS8555 device is specified over the extended industrial temperature range of –40°C to 125°C and is available in an LQFP-64 package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
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ADS8555 | LQFP (64) | 10.00 mm × 10.00 mm |
Changes from C Revision (October 2015) to D Revision
Changes from B Revision (February 2011) to C Revision
Changes from A Revision (January 2011) to B Revision
Changes from * Revision (December 2010) to A Revision
PIN | TYPE(1) | DESCRIPTION | ||
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NAME | NO. | |||
PARALLEL INTERFACE (PAR/SER = 0) | SERIAL INTERFACE (PAR/SER = 1) | |||
DB14/REFBUFEN | 1 | DIO/DI | Data bit 14 input/output | Hardware mode (HW/SW = 0): Reference buffers enable input. When low, all reference buffers are enabled (mandatory if internal reference is used). When high, all reference buffers are disabled. |
Software mode (HW/SW = 1):Connect to BGND or BVDD. The reference buffers are controlled by bit C24 (REFBUF) in control register (CR). |
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DB13/SDI | 2 | DIO/DI | Data bit 13 input/output | Hardware mode (HW/SW = 0): Connect to BGND |
Software mode (HW/SW = 1): Serial data input | ||||
DB12 | 3 | DIO | Data bit 12 input/output | Connect to BGND |
DB11 | 4 | DIO | Data bit 11 input/output | Connect to BGND |
DB10/SDO_C | 5 | DIO/DO | Data bit 10 input/output | When SEL_C = 1, data output for channel C When SEL_C = 0, tie this pin to BGND |
DB9/SDO_B | 6 | DIO/DO | Data bit 9 input/output | When SEL_B = 1, data output for channel B When SEL_B = 0, tie this pin to BGND When SEL_C = 0, data from channel C1 are also available on this output |
DB8/SDO_A | 7 | DIO/DO | Data bit 8 input/output | Data output for channel A When SEL_C = 0, data from channel C0 are also available on this output When SEL_C = 0 and SEL_B = 0, SDO_A acts as the single data output for all channels |
BGND | 8 | P | Buffer I/O ground, connect to digital ground plane | |
BVDD | 9 | P | Buffer I/O supply, connect to digital supply (2.7 V to 5.5 V). Decouple with a 1-μF ceramic capacitor or a combination of 100-nF and 10-μF ceramic capacitors to BGND. | |
DB7/HBEN/DCEN | 10 | DIO/DI/DI | Word mode (WORD/BYTE = 0): Data bit 7 input/output |
Daisy-chain enable input. When high, DB[5:3] serve as daisy-chain inputs DCIN[A:C]. If daisy-chain mode is not used, connect to BGND. |
Byte mode (WORD/BYTE = 1): High byte enable input. When high, the high byte is output first on DB[15:8]. When low, the low byte is output first on DB[15:8]. |
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DB6/SCLK | 11 | DIO/DI | Word mode (WORD/BYTE = 0): Data bit 6 input/output |
Serial interface clock input (36 MHz, max) |
Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD |
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DB5/DCIN_A | 12 | DIO/DI | Word mode (WORD/BYTE = 0): Data bit 5 input/output |
When DCEN = 1, daisy-chain data input for channel A When DCEN = 0, connect to BGND |
Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD |
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DB4/DCIN_B | 13 | DIO/DI | Word mode (WORD/BYTE = 0): Data bit 4 input/output |
When SEL_B = 1 and DCEN = 1, daisy-chain data input for channel B When DCEN = 0, connect to BGND |
Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD |
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DB3/DCIN_C | 14 | DIO/DI | Word mode (WORD/BYTE = 0): Data bit 3 input/output |
When SEL_C = 1 and DCEN = 1, daisy-chain data input for channel C When DCEN = 0, connect to BGND |
Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD |
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DB2/SEL_C | 15 | DIO/DI | Word mode (WORD/BYTE = 0): Data bit 2 input/output |
Select SDO_C input. When high, SDO_C is active. When low, SDO_C is disabled. |
Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD |
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DB1/SEL_B | 16 | DIO/DI | Word mode (WORD/BYTE = 0): Data bit 1 input/output |
Select SDO_B input. When high, SDO_B is active. When low, SDO_B is disabled. |
Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD |
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DB0/SEL_A | 17 | DIO/DI | Word mode (WORD/BYTE = 0): Data bit 0 (LSB) input/output |
Select SDO_A input. When high, SDO_A is active. When low, SDO_A is disabled. Must always be high. |
Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD |
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BUSY/INT | 18 | DO | When CR bit C21 = 0 (BUSY/INT), converter busy status output. Transitions high when a conversion starts and remains high during the entire process. Transitions low when the conversion data of all six channels are latched to the output register and remains low thereafter. In sequential mode (SEQ = 1 in the CR), the BUSY output transitions high when a conversion starts and goes low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion completes. When bit C21 = 1 (BUSY/INT in CR), interrupt output. This bit transitions high after a conversion completes and goes low with the first read data access. The polarity of BUSY/INT output can be changed using bit C20 (BUSY L/H) in the control register. |
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CS/FS | 19 | DI/DI | Chip select input. When low, the parallel interface is enabled. When high, the interface is disabled. |
Frame synchronization. The falling edge of FS controls the frame transfer. |
RD | 20 | DI | Read data input. When low, the parallel data output is enabled. When high, the data output is disabled. |
Connect to BGND |
CONVST_C | 21 | DI | Hardware mode (HW/SW = 0): Conversion start of channel pair C. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. |
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Software mode (HW/SW = 1): Conversion start of channel pair C in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise | ||||
CONVST_B | 22 | DI | Hardware mode (HW/SW = 0): Conversion start of channel pair B. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. |
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Software mode (HW/SW = 1): Conversion start of channel pair B in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise | ||||
CONVST_A | 23 | DI | Hardware mode (HW/SW = 0): Conversion start of channel pair A. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. |
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Software mode (HW/SW = 1): Conversion start of all selected channels except in sequential mode (CR bit C23 = 1): Conversion start of channel pair A only |
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STBY | 24 | DI | Standby mode input. When low, the entire device is powered down (including the internal clock and reference). When high, the device operates in normal mode. |
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AGND | 25, 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 | P | Analog ground, connect to analog ground plane Pin 25 can have a dedicated ground if the difference between its potential and AGND is always kept within ±300 mV. |
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AVDD | 26, 34, 35, 40, 41, 46, 47, 50, 60 | P | Analog power supply (4.5 V to 5.5 V). Decouple each pin with a 100-nF ceramic capacitor to AGND. Use an additional 10-μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. Pin 26 can have a dedicated power supply if the difference between its potential and AVDD is always kept within ±300 mV. | |
RANGE/XCLK | 27 | DI/DIO | Hardware mode (HW/SW = 0): Input voltage range select input. When low, the analog input range is ±4 VREF. When high, the analog input range is ±2 VREF. |
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Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND. | ||||
RESET | 28 | DI | Reset input, active high. Aborts any ongoing conversions. Resets the internal control register to 0x000003FF. The RESET pulse must be at least 50 ns long. | |
WORD/BYTE | 29 | DI | Output mode selection input. When low, data are transferred in word mode using DB[15:0]. When high, data are transferred in byte mode using DB[15:8] with the byte order controlled by HBEN pin when two accesses are required for a complete 16-bit transfer. |
Connect to BGND |
HVSS | 30 | P | Negative supply voltage for the analog inputs (–16.5 V to –5 V). Decouple with a 10-0nF ceramic capacitor to AGND placed next to the device and a 10-μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. |
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HVDD | 31 | P | Positive supply voltage for the analog inputs (5 V to 16.5 V). Decouple with a 100-nF ceramic capacitor to AGND placed next to the device and a 10-μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. | |
CH_A0 | 33 | AI | Analog input of channel A0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode. | |
CH_A1 | 36 | AI | Analog input of channel A1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode. | |
CH_B0 | 39 | AI | Analog input of channel B0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode. | |
CH_B1 | 42 | AI | Analog input of channel B1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode. | |
CH_C0 | 45 | AI | Analog input of channel C0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode. | |
CH_C1 | 48 | AI | Analog input of channel C1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode. | |
REFIO | 51 | AIO | Reference voltage input/output (0.5 V to 3.025 V). The internal reference is enabled through REFEN/WR pin in hardware mode or CR bit C25 (REFEN) in software mode. The output value is controlled by the internal DAC (CR bits C[9:0]). Connect a 470-nF ceramic decoupling capacitor between this pin and pin 52. |
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REFC_A | 54 | AI | Decoupling capacitor for reference of channels A. Connect a 10-μF ceramic decoupling capacitor between this pin and pin 53. |
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REFC_B | 56 | AI | Decoupling capacitor for reference of channels B. Connect a 10-μF ceramic decoupling capacitor between this pin and pin 55. |
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REFC_C | 58 | AI | Decoupling capacitor for reference of channels C. Connect a 10-μF ceramic decoupling capacitor between this pin and pin 57. |
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PAR/SER | 61 | DI | Interface mode selection input. When low, the parallel interface is selected. When high, the serial interface is enabled. |
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HW/SW | 62 | DI | Mode selection input. When low, the hardware mode is selected and the device works according to the settings of external pins. When high, the software mode is selected in which the device is configured by writing into the control register. |
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REFEN/WR | 63 | DI | Hardware mode (HW/SW = 0): Internal reference enable input. When high, the internal reference is enabled (the reference buffers are to be enabled). When low, the internal reference is disabled and an external reference is applied at REFIO. |
Hardware mode (HW/SW = 0): Internal reference enable input. When high, the internal reference is enabled (the reference buffers are to be enabled). When low, the internal reference is disabled and an external reference must be applied at REFIO. |
Software mode (HW/SW = 1): Write input. The parallel data input is enabled when CS and WR are low. The internal reference is enabled by the CR bit C25 (REFEN). |
Software mode (HW/SW = 1): Connect to BGND or BVDD. The internal reference is enabled by CR bit C25 (REFEN). |
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DB15 | 64 | DIO | Data bit 15 (MSB) input/output | Connect to BGND |
MIN | MAX | UNIT | ||
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Supply voltage, HVDD to AGND | –0.3 | 18 | V | |
Supply voltage, HVSS to AGND | –18 | 0.3 | V | |
Supply voltage, AVDD to AGND | –0.3 | 6 | V | |
Supply voltage, BVDD to BGND | –0.3 | 6 | V | |
Analog input voltage | HVSS – 0.3 | HVDD + 0.3 | V | |
Reference input voltage with respect to AGND | AGND – 0.3 | AVDD + 0.3 | V | |
Digital input voltage with respect to BGND | BGND – 0.3 | BVDD + 0.3 | V | |
Ground voltage difference AGND to BGND | ±0.3 | V | ||
Input current to all pins except supply | –10 | 10 | mA | |
Maximum virtual junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
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Supply voltage, AVDD to AGND | 4.5 | 5 | 5.5 | V | |
Supply voltage, BVDD to BGND | Low-voltage levels | 2.7 | 3 | 3.6 | V |
5-V logic levels | 4.5 | 5 | 5.5 | ||
Input supply voltage, HVDD to AGND | Input range = ±2 × VREF | 2 × VREF | 16.5 | V | |
Input range = ±4 × VREF | 4 × VREF | 16.5 | |||
Input supply voltage, HVSS to AGND | Input range = ±2 × VREF | –16.5 | –2 × VREF | V | |
Input range = ±4 × VREF | –16.5 | –4 × VREF | |||
Reference input voltage (VREF) | 0.5 | 2.5 | 3 | V | |
Analog inputs (also see the Analog Inputs section) |
Input range = ±2 × VREF | –2 × VREF | 2 × VREF | V | |
Input range = ±4 × VREF | –4 × VREF | 4 × VREF | |||
Operating ambient temperature, TA | –40 | 125 | °C |
THERMAL METRIC(1) | ADS8555 | UNIT | ||
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PM (LQFP) | ||||
64 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 48 | °C/W | |
RθJC(top) | Junction-to-case (top) thermal resistance | 16 | °C/W | |
RθJB | Junction-to-board thermal resistance | N/A | °C/W | |
ψJT | Junction-to-top characterization parameter | N/A | °C/W | |
ψJB | Junction-to-board characterization parameter | N/A | °C/W | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
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DC ACCURACY | ||||||
Resolution | 16 | Bits | ||||
No missing codes | 16 | Bits | ||||
Integral linearity error | INL | At TA = –40°C to 85°C | –3 | ±1.5 | 3 | LSB |
At TA = –40°C to 125°C | –4 | ±1.5 | 4 | |||
Differential linearity error | DNL | At TA = –40°C to 85°C | –1 | ±0.75 | 1.5 | LSB |
At TA = –40°C to 125°C | –1 | ±0.75 | 2 | |||
Offset error | –4 | ±0.8 | 4 | mV | ||
Offset error drift | ±3.5 | μV/°C | ||||
Gain error | Referenced to voltage at REFIO | –0.75 | ±0.25 | 0.75 | %FSR | |
Gain error drift | Referenced to voltage at REFIO | ±6 | ppm/°C | |||
Power-supply rejection ratio | PSRR | At output code FFFFh, related to AVDD | 60 | dB | ||
SAMPLING DYNAMICS | ||||||
Acquisition time | tACQ | 280 | ns | |||
Conversion time per ADC | tCONV | 1.26 | μs | |||
Internal conversion clock period | tCCLK | 18.5 | tCCLK | |||
68 | ns | |||||
Throughput rate | fDATA | Parallel interface, internal clock and reference | 630 | kSPS | ||
Serial interface, internal clock and reference | 450 | |||||
AC ACCURACY | ||||||
Signal-to-noise ratio | SNR | At fIN = 10 kHz, TA = –40°C to 85°C | 90 | 91.5 | dB | |
At fIN = 10 kHz, TA = –40°C to 125°C | 89 | 91.5 | ||||
Signal-to-noise ratio + distortion | SINAD | At fIN = 10 kHz, TA = –40°C to 85°C | 87 | 89.5 | dB | |
At fIN = 10 kHz, TA = –40°C to 125°C | 86.5 | 89.5 | ||||
Total harmonic distortion(2) | THD | At fIN = 10 kHz, TA = –40°C to 85°C | –94 | –90 | dB | |
At fIN = 10 kHz, TA = –40°C to 125°C | –94 | –89.5 | ||||
Spurious-free dynamic range | SFDR | At fIN = 10 kHz, TA = –40°C to 85°C | 90 | 95 | dB | |
At fIN = 10 kHz, TA = –40°C to 125°C | 89.5 | 95 | ||||
Channel-to-channel isolation | At fIN = 10 kHz | 100 | dB | |||
–3-dB small-signal bandwidth | Input range = ±4 × VREF | 48 | MHz | |||
Input range = ±2 × VREF | 24 | |||||
ANALOG INPUT | ||||||
Bipolar full-scale range | CHXX | RANGE pin, RANGE bit = 0 | –4 × VREF | 4 × VREF | V | |
RANGE pin, RANGE bit = 1 | –2 × VREF | 2 × VREF | ||||
Input capacitance | Input range = ±4 × VREF | 10 | pF | |||
Input range = ±2 × VREF | 20 | |||||
Input leakage current | No ongoing conversion | ±1 | μA | |||
Aperture delay | 5 | ns | ||||
Aperture delay matching | Common CONVST for all channels | 250 | ps | |||
Aperture jitter | 50 | ps | ||||
EXTERNAL CLOCK INPUT (XCLK) | ||||||
External clock frequency | fXCLK | An external reference must be used for fXCLK > fCCLK | 1 | 18 | 20 | MHz |
External clock duty cycle | 45% | 55% | ||||
REFERENCE VOLTAGE OUTPUT (REFOUT) | ||||||
Reference voltage | VREF | 2.5-V operation, REFDAC = 0x3FF | 2.485 | 2.5 | 2.515 | V |
2.5-V operation, REFDAC = 0x3FF at 25°C | 2.496 | 2.5 | 2.504 | |||
3-V operation, REFDAC = 0x3FF | 2.985 | 3 | 3.015 | |||
3-V operation, REFDAC = 0x3FF at 25°C | 2.995 | 3 | 3.005 | |||
Reference voltage drift | dVREF/dT | ±10 | ppm/°C | |||
Power-supply rejection ratio | PSRR | 73 | dB | |||
Output current | IREFOUT | With dc current | –2 | 2 | mA | |
Short circuit current(3) | IREFSC | 50 | mA | |||
Turnon settling time | tREFON | 10 | ms | |||
External load capacitance | At CREF_x pins | 4.7 | 10 | μF | ||
At REFIO pins | 100 | 470 | nF | |||
Tuning range | REFDAC | Internal reference output voltage range | 0.2 × VREF | VREF | V | |
REFDAC resolution | 10 | Bits | ||||
REFDAC differential nonlinearity | DNLDAC | –1 | ±0.1 | 1 | LSB | |
REFDAC integral nonlinearity | INLDAC | –2 | ±0.1 | 2 | LSB | |
REFDAC offset error | VOSDAC | VREF = 0.5 V (DAC = 0x0CC) | –4 | ±0.65 | 4 | LSB |
REFERENCE VOLTAGE INPUT (REFIN) | ||||||
Reference input voltage | VREFIN | 0.5 | 2.5 | 3.025 | V | |
Input resistance | 100 | MΩ | ||||
Input capacitance | 5 | pF | ||||
Reference input current | 1 | μA | ||||
SERIAL CLOCK INPUT (SCLK) | ||||||
Serial clock input frequency | fSCLK | 0.1 | 36 | MHz | ||
Serial clock period | tSCLK | 0.0278 | 10 | μs | ||
Serial clock duty cycle | 40% | 60% | ||||
DIGITAL INPUTS(4) | ||||||
Logic family | CMOS with Schmitt-Trigger | |||||
High-level input voltage | 0.7 × BVDD | BVDD + 0.3 | V | |||
Low-level input voltage | BGND – 0.3 | 0.3 × BVDD | V | |||
Input current | VI = BVDD to BGND | –50 | 50 | nA | ||
Input capacitance | 5 | pF | ||||
DIGITAL OUTPUTS(4) | ||||||
Logic family | CMOS | |||||
High-level output voltage | IOH = 100 μA | BVDD – 0.6 | BVDD | V | ||
Low-level output voltage | IOH = –100 μA | BGND | BGND + 0.4 | V | ||
High-impedance-state output current | –50 | 50 | nA | |||
Output capacitance | 5 | pF | ||||
Load capacitance | 30 | pF | ||||
POWER-SUPPLY REQUIREMENTS | ||||||
Analog supply voltage | AVDD | 4.5 | 5 | 5.5 | V | |
Buffer I/O supply voltage | BVDD | 2.7 | 3 | 5.5 | V | |
Input positive supply voltage | HVDD | 5 | 10 | 16.5 | V | |
Input negative supply voltage | HVSS | –16.5 | –10 | –5 | V | |
Analog supply current(5) | IAVDD | fDATA = maximum | 30 | 36 | mA | |
fDATA = 250 kSPS (auto-NAP mode) | 14 | 16.5 | ||||
Auto-NAP mode, no ongoing conversion, internal conversion clock |
4 | 6 | ||||
Power-down mode | 0.1 | 50 | μA | |||
Buffer I/O supply current(6) | IBVDD | fDATA = maximum | 0.9 | 2 | mA | |
fDATA = 250 kSPS (auto-NAP mode) | 0.5 | 1.5 | ||||
Auto-NAP mode, no ongoing conversion, internal conversion clock |
0.1 | 10 | μA | |||
Power-down mode | 0.1 | 10 | ||||
Input positive supply current(7) | IHVDD | fDATA = maximum | 3 | 3.5 | mA | |
fDATA = 250 kSPS (auto-NAP mode) | 1.6 | 2 | ||||
Auto-NAP mode, no ongoing conversion, internal conversion clock |
0.2 | 0.3 | μA | |||
Power-down mode | 0.1 | 10 | ||||
Input negative supply current(8) | IHVSS | fDATA = maximum | 3.6 | 4 | mA | |
fDATA = 250 kSPS (auto-NAP mode) | 1.8 | 2.2 | ||||
Auto-NAP mode, no ongoing conversion, internal conversion clock |
0.2 | 0.25 | μA | |||
Power-down mode | 0.1 | 10 | ||||
Power dissipation(9) | fDATA = maximum | 251.7 | 298.5 | mW | ||
fDATA = 250 kSPS (auto-NAP mode) | 122.5 | 150 | ||||
Auto-NAP mode, no ongoing conversion, internal conversion clock |
26 | 38.3 | ||||
Power-down mode | 3.8 | 580 | μW |
MIN | MAX | UNIT | ||
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tACQ | Acquisition time | 280 | ns | |
tCONV | Conversion time | 1.26 | µs | |
t1 | CONVST_x low time | 20 | ns | |
t2 | BUSY low to FS low time | 0 | ns | |
t3 | Bus access finished to next conversion start time | 40 | ns | |
tD1 | CONVST_x high to BUSY high delay | 5 | 20 | ns |
tD2 | FS low to SDO_x active delay | 5 | 12 | ns |
tD3 | SCLK rising edge to new data valid delay | 15 | ns | |
tD4 | FS high to SDO_x 3-state delay | 10 | ns | |
tH1 | Input data to SCLK falling edge hold time | 5 | ns | |
tH2 | Output data to SCLK rising edge hold time | 5 | ns | |
tS1 | Input data to SCLK falling edge setup time | 3 | ns | |
tS3 | CONVST_x high to XCLK falling or rising edge setup time | 6 | ns | |
tSCLK | Serial clock period | 0.0278 | 10 | μs |
MIN | MAX | UNIT | ||
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tACQ | Acquisition time | 280 | ns | |
tCONV | Conversion time | 1.26 | µs | |
t1 | CONVST_x low time | 20 | ns | |
t2 | BUSY low to CS low time | 0 | ns | |
t3 | Bus access finished to next conversion start time(2) | 40 | ns | |
t4 | CS low to RD low time | 0 | ns | |
t5 | RD high to CS high time | 0 | ns | |
t6 | RD pulse width | 30 | ns | |
t7 | Minimum time between two read accesses | 10 | ns | |
tD1 | CONVST_x high to BUSY high delay | 5 | 20 | ns |
tD5 | RD falling edge to output data valid delay | 20 | ns | |
tH3 | Output data to RD rising edge hold time | 5 | ns |
MIN | MAX | UNIT | ||
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t8 | CS low to WR low time | 0 | ns | |
t9 | WR low pulse duration | 15 | ns | |
t10 | WR high pulse duration | 10 | ns | |
t11 | WR high to CS high time | 0 | ns | |
tS2 | Output data to WR rising edge setup time | 5 | ns | |
tH4 | Data output to WR rising edge hold time | 5 | ns |
fIN = 10 kHz |
fIN = 10 kHz |