The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance and consume extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.
The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 PowerPAD™ package.
The device includes internal references and the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS4249 | VQFN (64) | 9.00 mm × 9.00 mm |
Changes from D Revision (May 2015) to E Revision
Changes from C Revision (July 2012) to D Revision
Changes from B Revision (September 2011) to C Revision
Changes from A Revision (September 2011) to B Revision
65 MSPS | 125 MSPS | 160 MSPS | 250 MSPS | |
---|---|---|---|---|
ADS422x 12-bit family |
ADS4222 | ADS4225 | ADS4226 | ADS4229 |
ADS424x 14-bit family |
ADS4242 | ADS4245 | ADS4246 | ADS4249 |
The ADS4249 is pin-compatible with the previous generation ADS62P49 data converter; this similar architecture enables easy migration. However, there are some important differences between the two device generations, summarized in Table 1.
ADS62P49 | ADS4249 |
---|---|
PINS | |
Pin 22 is NC (not connected) | Pin 22 is AVDD |
Pins 38 and 58 are DRVDD | Pins 38 and 58 are NC (do not connect, must be floated) |
Pins 39 and 59 are DRGND | Pins 39 and 59 are NC (do not connect, must be floated) |
SUPPLY | |
AVDD is 3.3 V | AVDD is 1.8 V |
DRVDD is 1.8 V | No change |
INPUT COMMON-MODE VOLTAGE | |
VCM is 1.5 V | VCM is 0.95 V |
SERIAL INTERFACE | |
Protocol: 8-bit register address and 8-bit register data | No change in protocol New serial register map |
EXTERNAL REFERENCE | |
Supported | Not supported |
NOTE:
The PowerPAD is connected to DRGND.PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 17 | I | Analog ground |
18 | |||
21 | |||
24 | |||
27 | |||
28 | |||
31 | |||
32 | |||
AVDD | 16 | I | Analog power supply |
22 | |||
33 | |||
34 | |||
CLKM | 26 | I | Differential clock negative input |
CLKP | 25 | I | Differential clock positive input |
CLKOUTP | 57 | O | Differential output clock, true |
CLKOUTM | 56 | O | Differential output clock, complement |
CTRL1 | 35 | I | Digital control input pins. Together, these pins control the various power-down modes. |
CTRL2 | 36 | ||
CTRL3 | 37 | ||
DA0M | 40 | O | Channel A differential output data pair, D0 and D1 multiplexed |
DA0P | 41 | ||
DA2M | 42 | O | Channel A differential output data D2 and D3 multiplexed |
DA2P | 43 | ||
DA4M | 44 | O | Channel A differential output data D4 and D5 multiplexed |
DA4P | 45 | ||
DA6M | 46 | O | Channel A differential output data D6 and D7 multiplexed |
DA6P | 47 | ||
DA8M | 50 | O | Channel A differential output data D8 and D9 multiplexed |
DA8P | 51 | ||
DA10M | 52 | O | Channel A differential output data D10 and D11 multiplexed |
DA10P | 53 | ||
DA12M | 54 | O | Channel A differential output data D12 and D13 multiplexed |
DA12P | 55 | ||
DB0M | 60 | O | Channel B differential output data pair, D0 and D1 multiplexed |
DB0P | 61 | ||
DB2M | 62 | O | Channel B differential output data D2 and D3 multiplexed |
DB2P | 63 | ||
DB4M | 2 | O | Channel B differential output data D4 and D5 multiplexed |
DB4P | 3 | ||
DB6M | 4 | O | Channel B differential output data D6 and D7 multiplexed |
DB6P | 5 | ||
DB8M | 6 | O | Channel B differential output data D8 and D9 multiplexed |
DB8P | 7 | ||
DB10M | 8 | O | Channel B differential output data D10 and D11 multiplexed |
DB10P | 9 | ||
DB12M | 10 | O | Channel B differential output data D12 and D13 multiplexed |
DB12P | 11 | ||
DRGND | 49 | I | Output buffer ground |
PAD | |||
DRVDD | 1 | I | Output buffer supply |
48 | |||
INM_A | 30 | I | Differential analog negative input, channel A |
INP_A | 29 | I | Differential analog positive input, channel A |
INM_B | 20 | I | Differential analog negative input, channel B |
INP_B | 19 | I | Differential analog positive input, channel B |
NC | 38 | — | Do not connect, must be floated |
39 | |||
58 | |||
59 | |||
RESET | 12 | I | Serial interface RESET input. When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface Configuration section. In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down resistor. |
SCLK | 13 | I | This pin functions as a serial interface clock input when RESET is low. SCLK controls the low-speed mode selection when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-kΩ pull-down resistor. |
SDATA | 14 | I | Serial interface data input; this pin has an internal 150-kΩ pull-down resistor. |
SDOUT | 64 | O | This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is put into a high-impedance state. |
SEN | 15 | I | This pin functions as a serial interface enable input when RESET is low. SEN controls the output interface and data format selection when RESET is tied high; see Table 8 for detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD. |
VCM | 23 | O | This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins |
NOTE:
The PowerPAD is connected to DRGND.PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 17 | I | Analog ground |
18 | |||
21 | |||
24 | |||
27 | |||
28 | |||
31 | |||
32 | |||
AVDD | 16 | I | Analog power supply |
22 | |||
33 | |||
34 | |||
CLKM | 26 | I | Differential clock negative input |
CLKP | 25 | I | Differential clock positive input |
CLKOUT | 57 | O | CMOS output clock |
CTRL1 | 35 | I | Digital control input pins. Together, these pins control various power-down modes. |
CTRL2 | 36 | ||
CTRL3 | 37 | ||
DA0 | 40 | O | Channel A ADC output data bits, CMOS levels |
DA1 | 41 | ||
DA2 | 42 | ||
DA3 | 43 | ||
DA4 | 44 | ||
DA5 | 45 | ||
DA6 | 46 | ||
DA7 | 47 | ||
DA8 | 50 | ||
DA9 | 51 | ||
DA10 | 52 | ||
DA11 | 53 | ||
DA12 | 54 | ||
DA13 | 55 | ||
DB0 | 60 | O | Channel B ADC output data bits, CMOS levels |
DB1 | 61 | ||
DB2 | 62 | ||
DB3 | 63 | ||
DB4 | 2 | ||
DB5 | 3 | ||
DB6 | 4 | ||
DB7 | 5 | ||
DB8 | 6 | ||
DB9 | 7 | ||
DB10 | 8 | ||
DB11 | 9 | ||
DB12 | 10 | ||
DB13 | 11 | ||
DRGND | 49 | I | Output buffer ground |
PAD | |||
DRVDD | 1 | I | Output buffer supply |
48 | |||
INM_A | 30 | I | Differential analog negative input, channel A |
INP_A | 29 | I | Differential analog positive input, channel A |
INM_B | 20 | I | Differential analog negative input, channel B |
INP_B | 19 | I | Differential analog positive input, channel B |
NC | 38 | — | Do not connect, must be floated |
39 | |||
58 | |||
59 | |||
RESET | 12 | I | Serial interface RESET input. When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface Configuration section. In parallel interface mode, the RESET pin must be permanently tied high. SDATA and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down resistor. |
SCLK | 13 | I | This pin functions as a serial interface clock input when RESET is low. SCLK controls the low-speed mode when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-kΩ pull-down resistor. |
SDATA | 14 | I | Serial interface data input; this pin has an internal 150-kΩ pull-down resistor. |
SDOUT | 64 | O | This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is put into a high-impedance state. |
SEN | 15 | I | This pin functions as a serial interface enable input when RESET is low. SEN controls the output interface and data format selection when RESET is tied high; see Table 8 for detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD. |
UNUSED | 56 | — | This pin is not used in the CMOS interface |
VCM | 23 | O | This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, AVDD | –0.3 | 2.1 | V | |
Supply voltage, DRVDD | –0.3 | 2.1 | V | |
Voltage between AGND and DRGND | –0.3 | 0.3 | V | |
Voltage between AVDD to DRVDD (when AVDD leads DRVDD) | –2.4 | 2.4 | V | |
Voltage between DRVDD to AVDD (when DRVDD leads AVDD) | –2.4 | 2.4 | V | |
Voltage applied to input pins | INP_A, INM_A, INP_B, INM_B | –0.3 | Minimum (1.9, AVDD + 0.3) |
V |
CLKP, CLKM(2) | –0.3 | AVDD + 0.3 | ||
RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3 |
–0.3 | 3.9 | ||
Operating free-air temperature, TA | –40 | 85 | °C | |
Operating junction temperature, TJ | 125 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
SUPPLIES | |||||
Analog supply voltage, AVDD | 1.7 | 1.8 | 1.9 | V | |
Digital supply voltage, DRVDD | 1.7 | 1.8 | 1.9 | V | |
ANALOG INPUTS | |||||
Differential input voltage | 2 | VPP | |||
Input common-mode | VCM ± 0.05 | V | |||
Maximum analog input frequency with 2-VPP input amplitude(1) | 400 | MHz | |||
Maximum analog input frequency with 1-VPP input amplitude(1) | 600 | MHz | |||
CLOCK INPUT | |||||
Input clock sample rate | Low-speed mode enabled(2) | 1 | 80 | MSPS | |
Low-speed mode disabled(2) (by default after reset) | 80 | 250 | |||
Input clock amplitude differential (VCLKP – VCLKM) |
Sine wave, ac-coupled | 0.2 | 1.5 | VPP | |
LVPECL, ac-coupled | 1.6 | ||||
LVDS, ac-coupled | 0.7 | ||||
LVCMOS, single-ended, ac-coupled | 1.5 | ||||
Input clock duty cycle | Low-speed mode disabled | 35% | 50% | 65% | |
Low-speed mode enabled | 40% | 50% | 60% | ||
DIGITAL OUTPUTS | |||||
Maximum external load capacitance from each output pin to DRGND, CLOAD | 5 | pF | |||
Differential load resistance between the LVDS output pairs (LVDS mode), RLOAD | 100 | Ω | |||
Operating free-air temperature, TA | –40 | +85 | °C |
THERMAL METRIC(1) | ADS4249 | UNIT | |
---|---|---|---|
RGC (VQFN) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 23.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 10.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 4.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 4.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.6 | °C/W |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
ANALOG INPUTS | |||||
Differential input voltage range | 2 | VPP | |||
Differential input resistance (at 200 MHz) | 0.75 | kΩ | |||
Differential input capacitance (at 200 MHz) | 3.7 | pF | |||
Analog input bandwidth (with 50-Ω source impedance, and 50-Ω termination) |
550 | MHz | |||
Analog input common-mode current (per input pin of each channel) |
1.5 | µA/MSPS | |||
VCM | Common-mode output voltage | 0.95(2) | V | ||
VCM output current capability | 4 | mA | |||
DC ACCURACY | |||||
Offset error | –15 | 2.5 | 15 | mV | |
Temperature coefficient of offset error | 0.003 | mV/°C | |||
EGREF | Gain error as a result of internal reference inaccuracy alone | –2 | 2 | %FS | |
EGCHAN | Gain error of channel alone | ±0.1 | 1 | %FS | |
Temperature coefficient of EGCHAN | 0.002 | Δ%/°C | |||
POWER SUPPLY | |||||
IAVDD | Analog supply current | 167 | 190 | mA | |
IDRVDD | Output buffer supply current, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz | 144 | 160 | mA | |
IDRVDD | Output buffer supply current, CMOS interface, no load capacitance, fIN = 2.5 MHz(1) | 94 | mA | ||
Analog power | 301 | 342 | mW | ||
Digital power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz | 259 | 288 | mW | ||
Digital power, CMOS interface, 8-pF external load capacitance(1), fIN = 2.5 MHz |
169 | mW | |||
Global power-down | 25 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1) | ||||||
High-level input voltage | All digital inputs support 1.8-V and 3.3-V CMOS logic levels | 1.3 | V | |||
Low-level input voltage | 0.4 | V | ||||
High-level input current | SDATA, SCLK(2) | VHIGH = 1.8 V | 10 | µA | ||
SEN(3) | VHIGH = 1.8 V | 0 | ||||
Low-level input current | SDATA, SCLK | VLOW = 0 V | 0 | µA | ||
SEN | VLOW = 0 V | 10 | ||||
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT) | ||||||
High-level output voltage | DRVDD – 0.1 | DRVDD | V | |||
Low-level output voltage | 0 | 0.1 | V | |||
DIGITAL OUTPUTS, LVDS INTERFACE | ||||||
High-level output differential voltage |
VODH | With an external 100-Ω termination |
270 | 350 | 430 | mV |
Low-level output differential voltage |
VODL | With an external 100-Ω termination |
–430 | –350 | –270 | mV |
Output common-mode voltage | VOCM | 0.9 | 1.05 | 1.25 | V |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
GENERAL | ||||||
tA | Aperture delay | 0.5 | 0.8 | 1.1 | ns | |
Aperture delay matching between the two channels of the same device | ±70 | ps | ||||
Variation of aperture delay between two devices at the same temperature and DRVDD supply | ±150 | ps | ||||
tJ | Aperture jitter | 140 | fS rms | |||
Wakeup time | Time to valid data after coming out of STANDBY mode | 50 | 100 | µs | ||
Time to valid data after coming out of GLOBAL power-down mode | 100 | 500 | ||||
ADC latency(4) | Default latency after reset | 16 | Clock cycles | |||
Digital functions enabled (EN DIGITAL = 1) | 24 | |||||
DDR LVDS MODE(2) | ||||||
tSU | Data setup time: data valid(3) to zero-crossing of CLKOUTP | 0.6 | 0.88 | ns | ||
tH | Data hold time: zero-crossing of CLKOUTP to data becoming invalid(3) | 0.33 | 0.55 | ns | ||
tPDI | Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over | 5 | 6 | 7.5 | ns | |
LVDS bit clock duty cycle of differential clock, (CLKOUTP-CLKOUTM) | 48% | |||||
tRISE, tFALL |
Data rise time, data fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS |
0.13 | ns | |||
tCLKRISE, tCLKFALL |
Output clock rise time, output clock fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS | 0.13 | ns | |||
PARALLEL CMOS MODE | ||||||
tPDI | Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over | 4.5 | 6.2 | 8.5 | ns | |
Output clock duty cycle of output clock (CLKOUT), 1 MSPS ≤ sampling frequency ≤ 200 MSPS |
50% | |||||
tRISE, tFALL |
Data rise time, data fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 200 MSPS |
0.7 | ns | |||
tCLKRISE, tCLKFALL |
Output clock rise time output clock fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 200 MSPS | 0.7 | ns |
SAMPLING FREQUENCY (MSPS) | SETUP TIME (ns) | HOLD TIME (ns) | tPDI, CLOCK PROPAGATION DELAY (ns) |
||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | |
65 | 5.9 | 6.6 | 0.35 | 0.6 | 5 | 6 | 7.5 | ||
80 | 4.5 | 5.2 | 0.35 | 0.6 | 5 | 6 | 7.5 | ||
125 | 2.3 | 2.9 | 0.35 | 0.6 | 5 | 6 | 7.5 | ||
160 | 1.5 | 2 | 0.33 | 0.55 | 5 | 6 | 7.5 | ||
185 | 1.3 | 1.6 | 0.33 | 0.55 | 5 | 6 | 7.5 | ||
200 | 1.1 | 1.4 | 0.33 | 0.55 | 5 | 6 | 7.5 | ||
230 | 0.76 | 1.06 | 0.33 | 0.55 | 5 | 6 | 7.5 |
SAMPLING FREQUENCY (MSPS) | TIMINGS SPECIFIED WITH RESPECT TO CLKOUT | ||||||||
---|---|---|---|---|---|---|---|---|---|
SETUP TIME(1) (ns) | HOLD TIME(1) (ns) | tPDI, CLOCK PROPAGATION DELAY (ns) |
|||||||
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | |
65 | 6.1 | 6.7 | 6.7 | 7.5 | 4.5 | 6.2 | 8.5 | ||
80 | 4.7 | 5.2 | 5.3 | 6 | 4.5 | 6.2 | 8.5 | ||
125 | 2.7 | 3.1 | 3.1 | 3.6 | 4.5 | 6.2 | 8.5 | ||
160 | 1.6 | 2.1 | 2.3 | 2.8 | 4.5 | 6.2 | 8.5 | ||
185 | 1.1 | 1.6 | 1.9 | 2.4 | 4.5 | 6.2 | 8.5 | ||
200 | 1 | 1.4 | 1.7 | 2.2 | 4.5 | 6.2 | 8.5 |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency (equal to 1 / tSCLK) | > dc | 20 | MHz | |
tSLOADS | SEN to SCLK setup time | 25 | ns | ||
tSLOADH | SCLK to SEN hold time | 25 | ns | ||
tDSU | SDATA setup time | 25 | ns | ||
tDH | SDATA hold time | 25 | ns |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
t1 | Power-on delay from AVDD and DRVDD power-up to active RESET pulse | 1 | ms | ||
t2 | Reset pulse duration; active RESET signal pulse duration | 10 | ns | ||
1 | µs | ||||
t3 | Register write delay from RESET disable to SEN active | 100 | ns |
NOTE:
A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel interface operation, RESET must be permanently tied high.The ADS4249 belongs to TI's ultralow power family of dual-channel, 14-bit analog-to-digital converters (ADCs). High performance is maintained when reducing power for power sensitive applications. In addition to its low power and high performance, the ADS4249 has a number of digital features and operating modes to enable design flexibility.
The device has several useful digital functions (such as test patterns, gain, and offset correction). These functions require extra clock cycles for operation and increase the overall latency and power of the device. These digital functions are disabled by default after reset and the raw ADC output is routed to the output data pins with a latency of 16 clock cycles. Figure 37 shows more details of the processing after the ADC. In order to use any of the digital functions, the EN DIGITAL bit must be set to '1'. After this, the respective register bits must be programmed as described in the following sections and in the Serial Register Map section.
The ADS4249 includes gain settings that can be used to get improved SFDR performance (compared to no gain). The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 2.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB.
GAIN (dB) | TYPE | FULL-SCALE (VPP) |
---|---|---|
0 | Default after reset | 2 |
1 | Fine, programmable | 1.78 |
2 | Fine, programmable | 1.59 |
3 | Fine, programmable | 1.42 |
4 | Fine, programmable | 1.26 |
5 | Fine, programmable | 1.12 |
6 | Fine, programmable | 1 |
The ADS4249 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The correction can be enabled using the ENABLE OFFSET CORR serial register bit. When enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 3.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 0. When frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by default after reset.
OFFSET CORR TIME CONSTANT | TIME CONSTANT, TCCLK
(Number of Clock Cycles) |
TIME CONSTANT, TCCLK × 1/fS (ms)(1) |
---|---|---|
0000 | 1 M | 4 |
0001 | 2 M | 8 |
0010 | 4 M | 16 |
0011 | 8 M | 32 |
0100 | 16 M | 64 |
0101 | 32 M | 128 |
0110 | 64 M | 256 |
0111 | 128 M | 512 |
1000 | 256 M | 1024 |
1001 | 512 M | 2048 |
1010 | 1 G | 4096 |
1011 | 2 G | 8192 |
1100 | Reserved | — |
1101 | Reserved | — |
1110 | Reserved | — |
1111 | Reserved | — |
The ADS4249 has two power-down modes: global power-down and channel standby. These modes can be set using either the serial register bits or using the control pins CTRL1 to CTRL3 (as shown in Table 4).
CTRL1 | CTRL2 | CTRL3 | DESCRIPTION |
---|---|---|---|
Low | Low | Low | Default |
Low | Low | High | Not available |
Low | High | Low | Not available |
Low | High | High | Not available |
High | Low | Low | Global power-down |
High | Low | High | Channel A powered down, channel B is active |
High | High | Low | Not available |
High | High | High | MUX mode of operation, channel A and B data is multiplexed and output on DB[13:0] pins |
In this mode, the entire chip (including ADCs, internal reference, and output buffers) are powered down, resulting in reduced total power dissipation of approximately 20 mW when the CTRL pins are used and 3mW when the PDN GLOBAL serial register bit is used. The output buffers are in high-impedance state. The wake-up time from global power-down to data becoming valid in normal mode is typically 100 µs.
In this mode, each ADC channel can be powered down. The internal references are active, resulting in a quick wake-up time of 50 µs. The total power dissipation in standby is approximately 240 mW at 250 MSPS.
In addition to the previous modes, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The power dissipation is approximately 160 mW.
Two output data formats are supported: twos complement and offset binary. The format can be selected using the DATA FORMAT serial interface register bit or by controlling the DFS pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 3FFFh for the ADS4249 in offset binary output format; the output code is 1FFFh for the ADS4249 in twos complement output format. For a negative input overdrive, the output code is 0000h in offset binary output format and 2000h for the ADS4249 in twos complement output format.
The ADS4249 provides 14-bit digital data for each channel and an output clock synchronized with the data.
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the serial interface register bit or by setting the proper voltage on the SEN pin in parallel configuration mode.
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 38.
Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3, D5, and so forth) are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be used to capture all the data bits, as shown in Figure 39.
The equivalent circuit of each LVDS output buffer is shown in Figure 40. After reset, the buffer presents an output impedance of 100Ω to match with the external 100-Ω termination.
NOTE:
Default swing across 100-Ω load is ±350 mV. Use the LVDS SWING bits to change the swing.The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination, as shown in Figure 41. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. Absorbing reflections from the receiver end helps improve signal integrity.
In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle, as Figure 42 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Minimizing the load capacitance of the data and clock output pins is recommended by using short traces to the receiver. Furthermore, match the output data and clock traces to minimize the skew between them.
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. This relationship is shown by Equation 1:
where
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (DB[11:0] pins), as shown in Figure 43. The channel A output pins (DA[11:0]) are in 3-state. Because the output data rate on the DB bus is effectively doubled, this mode is recommended only for low sampling frequencies (less than 80 MSPS). This mode can be enabled using the POWER-DOWN MODE register bits or using the CTRL[3:1] parallel pins.
The ADS4249 can be configured independently using either parallel interface control or serial interface programming. Table 5 lists the device high-performance modes.
PARAMETER | DESCRIPTION |
---|---|
High-performance mode | Set the HIGH PERF MODE[2:1] register bit to obtain best performance across sample clock and input signal frequencies. Register address = 03h, data = 03h |
High-frequency mode | Set the HIGH FREQ MODE CH A and HIGH FREQ MODE CH B register bits for high input signal frequencies greater than 200 MHz. Register address = 4Ah, data = 01h Register address = 58h, data = 01h |
High-speed mode | Set the HIGH PERF MODE[8:3] bits to obtain best performance across input signal frequencies for sampling rates greater than 160 MSPS. Note that this mode changes VCM to 0.87 V from its default value of 0.95 V. Register address = 2h, data = 40h Register address = D5h, data = 18h Register address = D7h, data = 0Ch Register address = DBh, data = 20h |
To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK, CTRL1, CTRL2, and CTRL3 pins to directly control certain modes of the ADC. The device can be easily configured by connecting the parallel pins to the correct voltage levels (as described in Table 6 to Table 9). There is no need to apply a reset and SDATA can be connected to ground.
In this mode, SEN and SCLK function as parallel interface control pins. Some frequently-used functions can be controlled using these pins. Table 6 describes the modes controlled by the parallel pins.
PIN | CONTROL MODE |
---|---|
SCLK | Low-speed mode selection |
SEN | Output data format and output interface selection |
CTRL1 | Together, these pins control the power-down modes |
CTRL2 | |
CTRL3 |
To enable this mode, the serial registers must first be reset to the default values and the RESET pin must be kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by setting the RESET bit high. The Serial Register Map section describes the register programming and the register reset process in more detail.
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3) can also be used to configure the device. To enable this option, keep RESET low. The parallel interface control pins CTRL1 to CTRL3 are available. After power-up, the device is automatically configured according to the voltage settings on these pins (see Table 9). SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of the ADC. The registers must first be reset to the default values either by applying a pulse on the RESET pin or by setting the RESET bit to '1'. After reset, the RESET pin must be kept low. The Serial Register Map section describes register programming and the register reset process in more detail.
The functions controlled by each parallel pin are described in Table 7, Table 8, and Table 9. A simple way of configuring the parallel pins is shown in Figure 44.
VOLTAGE APPLIED ON SCLK | DESCRIPTION |
---|---|
Low | Low-speed mode is disabled |
High | Low-speed mode is enabled |
VOLTAGE APPLIED ON SEN | DESCRIPTION |
---|---|
0 (50 mV / 0 mV) |
Twos complement and parallel CMOS output |
(3/8) AVDD (±50 mV) |
Offset binary and parallel CMOS output |
(5/8) 2AVDD (±5 0mV) |
Offset binary and DDR LVDS output |
AVDD (0 mV / –50 mV) |
Twos complement and DDR LVDS output |
CTRL1 | CTRL2 | CTRL3 | DESCRIPTION |
---|---|---|---|
Low | Low | Low | Normal operation |
Low | Low | High | Not available |
Low | High | Low | Not available |
Low | High | High | Not available |
High | Low | Low | Global power-down |
High | Low | High | Channel A standby, channel B is active |
High | High | Low | Not available |
High | High | High | MUX mode of operation, channel A and B data are multiplexed and output on the DB[13:0] pins. See the Multiplexed Mode of Operation section for further details. |
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty cycle.
After power-up, the internal registers must be initialized to the default values. Initialization can be accomplished in one of two ways:
The device includes a mode where the contents of the internal registers can be read back. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. To use readback mode, follow this procedure:
The serial register readout works with both CMOS and LVDS interfaces on pin 64. Figure 45 shows the serial readout timing diagram.
When READOUT is disabled, the SDOUT pin is in high-impedance state.
Table 10 summarizes the functions supported by the serial interface.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | RESET | READOUT |
Bits[7:2] | Always write '0' |
Bit 1 | RESET: Software reset applied |
This bit resets all internal registers to the default values and self-clears to 0 (default = 1). | |
Bit 0 | READOUT: Serial readout |
This bit sets the serial readout of the registers. 0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance state. 1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS logic levels running from the DRVDD supply. See the Serial Register Readout section. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LVDS SWING | 0 | 0 |
Bits[7:2] | LVDS SWING: LVDS swing programmability |
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming swing. 000000 = Default LVDS swing; ±350 mV with external 100-Ω termination 011011 = LVDS swing ±410 mV 110010 = LVDS swing ±465 mV 010100 = LVDS swing ±570 mV 111110 = LVDS swing ±200 mV 001111 = LVDS swing ±125 mV |
|
Bits[1:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH PERF MODE 2 | HIGH PERF MODE 1 |
Bits[7:2] | Always write '0' |
Bits[1:0] | HIGH PERF MODE[2:1]: High-performance mode |
00 = Default performance 01 = Do not use 10 = Do not use 11 = Obtain best performance across sample clock and input signal frequencies |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH A GAIN | 0 | CH A TEST PATTERNS |
Bits[7:4] | CH A GAIN: Channel A gain programmability | ||
These bits set the gain programmability in 0.5-dB steps for channel A. | |||
0000 = 0-dB gain (default after reset) 0001 = 0.5-dB gain 0010 = 1-dB gain 0011 = 1.5-dB gain 0100 = 2-dB gain 0101 = 2.5-dB gain 0110 = 3-dB gain 0111 = 3.5-dB gain 1000 = 4-dB gain 1001 = 4.5-dB gain 1010 = 5-dB gain 1011 = 5.5-dB gain 1100 = 6-dB gain |
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Bit 3 | Always write '0' | ||
Bits[2:0] | CH A TEST PATTERNS: Channel A data capture | ||
These bits verify data capture for channel A. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern. The output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101. 100 = Outputs digital ramp. 101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern 110 = Unused 111 = Unused |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | DATA FORMAT | 0 | 0 | 0 |
Bits[7:5] | Always write '0' | ||
Bits[4:3] | DATA FORMAT: Data format selection | ||
00 = Twos complement 01 = Twos complement 10 = Twos complement 11 = Offset binary |
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Bits[2:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH B GAIN | 0 | CH B TEST PATTERNS |
Bits[7:4] | CH B GAIN: Channel B gain programmability | ||
These bits set the gain programmability in 0.5-dB steps for channel B. | |||
0000 = 0-dB gain (default after reset) 0001 = 0.5-dB gain 0010 = 1-dB gain 0011 = 1.5-dB gain 0100 = 2-dB gain 0101 = 2.5-dB gain 0110 = 3-dB gain 0111 = 3.5-dB gain 1000 = 4-dB gain 1001 = 4.5-dB gain 1010 = 5-dB gain 1011 = 5.5-dB gain 1100 = 6-dB gain |
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Bit 3 | Always write '0' | ||
Bits[2:0] | CH B TEST PATTERNS: Channel B data capture | ||
These bits verify data capture for channel B. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern. The output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101. 100 = Outputs digital ramp. 101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern 110 = Unused 111 = Unused |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | ENABLE OFFSET CORR | 0 | 0 | 0 | 0 | 0 |
Bits[7:6] | Always write '0' |
Bit 5 | ENABLE OFFSET CORR: Offset correction setting |
This bit enables the offset correction. 0 = Offset correction disabled 1 = Offset correction enabled |
|
Bits[4:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | CUSTOM PATTERN D13 | CUSTOM PATTERN D12 | CUSTOM PATTERN D11 | CUSTOM PATTERN D10 | CUSTOM PATTERN D9 | CUSTOM PATTERN D8 |
Bits[7:6] | Always write '0' |
Bits[5:0] | CUSTOM PATTERN D[13:8] |
These are the six upper bits of the custom pattern available at the output instead of ADC data. The ADS4249 custom pattern is 14-bit. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM PATTERN D7 | CUSTOM PATTERN D6 | CUSTOM PATTERN D5 | CUSTOM PATTERN D4 | CUSTOM PATTERN D3 | CUSTOM PATTERN D2 | CUSTOM PATTERN D1 | CUSTOM PATTERN D0 |
Bits[7:0] | CUSTOM PATTERN D[7:0] |
These are the eight lower bits of the custom pattern available at the output instead of ADC data. The ADS4249 custom pattern is 14-bit; use the CUSTOM PATTERN D[13:0] register bits. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LVDS CMOS | CMOS CLKOUT STRENGTH | 0 | 0 | DIS OBUF |
Bits[7:6] | LVDS CMOS: Interface selection |
These bits select the interface. 00 = DDR LVDS interface 01 = DDR LVDS interface 10 = DDR LVDS interface 11 = Parallel CMOS interface |
|
Bits[5:4] | CMOS CLKOUT STRENGTH |
These bits control the strength of the CMOS output clock. 00 = Maximum strength (recommended) 01 = Medium strength 10 = Low strength 11 = Very low strength |
|
Bits[3:2] | Always write '0' |
Bits[1:0] | DIS OBUF |
These bits power down data and clock output buffers for both the CMOS and LVDS output interface. When powered down, the output buffers are in 3-state. 00 = Default 01 = Power-down data output buffers for channel B 10 = Power-down data output buffers for channel A 11 = Power-down data output buffers for both channels as well as the clock output buffer |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKOUT FALL POSN | CLKOUT RISE POSN | EN DIGITAL | 0 | 0 | 0 |
Bits[7:6] | CLKOUT FALL POSN |
In LVDS mode: 00 = Default 01 = The falling edge of the output clock advances by 450 ps 10 = The falling edge of the output clock advances by 150 ps 11 = The falling edge of the output clock is delayed by 550 ps In CMOS mode: 00 = Default 01 = The falling edge of the output clock is delayed by 150 ps 10 = Do not use 11 = The falling edge of the output clock advances by 100 ps |
|
Bits[5:6] | CLKOUT RISE POSN |
In LVDS mode: 00 = Default 01 = The rising edge of the output clock advances by 450 ps 10 = The rising edge of the output clock advances by 150 ps 11 = The rising edge of the output clock is delayed by 250 ps In CMOS mode: 00 = Default 01 = The rising edge of the output clock is delayed by 150 ps 10 = Do not use 11 = The rising edge of the output clock advances by 100 ps |
|
Bit 3 | EN DIGITAL: Digital function enable |
0 = All digital functions disabled 1 = All digital functions (such as test patterns, gain, and offset correction) enabled |
|
Bits[2:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STBY | LVDS CLKOUT STRENGTH | LVDS DATA STRENGTH | 0 | 0 | PDN GLOBAL | 0 | 0 |
Bit 7 | STBY: Standby setting | ||
0 = Normal operation 1 = Both channels are put in standby; wakeup time from this mode is fast (typically 50 µs). |
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Bit 6 | LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting | ||
0 = LVDS output clock buffer at default strength to be used with 100-Ω external termination 1 = LVDS output clock buffer has double strength to be used with 50-Ω external termination |
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Bit 5 | LVDS DATA STRENGTH | ||
0 = All LVDS data buffers at default strength to be used with 100-Ω external termination 1 = All LVDS data buffers have double strength to be used with 50-Ω external termination |
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Bits[4:3] | Always write '0' | ||
Bit 2 | PDN GLOBAL | ||
0 = Normal operation 1 = Total power down; all ADC channels, internal references, and output buffers are powered down. Wakeup time from this mode is slow (typically 100 µs). |
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Bits[1:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | HIGH FREQ MODE CH B |
Bits[7:1] | Always write '0' | ||
Bit 0 | HIGH FREQ MODE CH B: High-frequency mode for channel B | ||
0 = Default 1 = Use this mode for high input frequencies greater than 200 MHz |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | HIGH FREQ MODE CH A |
Bits[7:1] | Always write '0' | ||
Bit 0 | HIGH FREQ MODE CH A: High-frequency mode for channel A | ||
0 = Default 1 = Use this mode for high input frequencies greater than 200 MHz |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH A OFFSET PEDESTAL | 0 | 0 |
Bits[7:4] | CH A OFFSET PEDESTAL: Channel A offset pedestal selection | ||
When the offset correction is enabled, the final converged value after the offset is corrected is the ADC midcode value. A pedestal can be added to the final converged value by programming these bits. See the Offset Correction section. Channels can be independently programmed for different offset pedestals by choosing the relevant register address. The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to midcode+31 by adding pedestal D7-D2. |
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Program bits D[7:2] | |||
011111 = Midcode+31 011110 = Midcode+30 011101 = Midcode+29 … 000010 = Midcode+2 000001 = Midcode+1 000000 = Midcode 111111 = Midcode-1 111110 = Midcode-2 … 100000 = Midcode-32 |
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Bits[3:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH B OFFSET PEDESTAL | 0 | 0 |
Bits[7:4] | CH B OFFSET PEDESTAL: Channel B offset pedestal selection | |
When offset correction is enabled, the final converged value after the offset is corrected is the ADC midcode value. A pedestal can be added to the final converged value by programming these bits; see the Offset Correction section. Channels can be independently programmed for different offset pedestals by choosing the relevant register address. The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to midcode+31 by adding pedestal D7-D2. |
||
Program Bits D[7:2] | ||
011111 = Midcode+31 011110 = Midcode+30 011101 = Midcode+29 … 000010 = Midcode+2 000001 = Midcode+1 000000 = Midcode 111111 = Midcode-1 111110 = Midcode-2 … 100000 = Midcode-32 |
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Bits[3:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREEZE OFFSET CORR | 0 | OFFSET CORR TIME CONSTANT | 0 | 0 |
Bit 7 | FREEZE OFFSET CORR: Freeze offset correction setting | |
This bit sets the freeze offset correction estimation. 0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set) 1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen, the last estimated value is used for offset correction of every clock cycle. See the Offset Correction section. |
||
Bit 6 | Always write '0' | |
Bits[5:2] | OFFSET CORR TIME CONSTANT | |
The offset correction loop time constant in number of clock cycles. See the Offset Correction section. | ||
Bits[1:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | EN LOW SPEED MODE | 0 | 0 | 0 | 0 |
Bits[7:5] | Always write '0' |
Bit 4 | EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits |
This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and LOW SPEED MODE CH A register bits. 0 = Low-speed mode is disabled 1 = Low-speed mode is controlled by serial register bits |
|
Bits[3:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | EN LVDS SWING |
Bits[7:2] | Always write '0' |
Bits[1:0] | EN LVDS SWING: LVDS swing enable |
These bits enable LVDS swing control using the LVDS SWING register bits. 00 = LVDS swing control using the LVDS SWING register bits is disabled 01 = Do not use 10 = Do not use 11 = LVDS swing control using the LVDS SWING register bits is enabled |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | LOW SPEED MODE CH A | 0 | 0 | 0 |
Bits[7:4] | Always write '0' |
Bit 3 | LOW SPEED MODE CH A: Channel A low-speed mode enable |
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to '1' before using this bit. 0 = Low-speed mode is disabled for channel A 1 = Low-speed mode is enabled for channel A |
|
Bits[2:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | HIGH PERF MODE3 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 | Always write '0' |
Bit 6 | HIGH PERF MODE3 |
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high sampling speed (greater than 160 MSPS) | |
Bits[5:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | HIGH PERF MODE4 | HIGH PERF MODE5 | 0 | 0 | 0 |
Bits[7:5] | Always write '0' |
Bit 4 | HIGH PERF MODE4 |
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high sampling speed (greater than 160 MSPS) | |
Bit 3 | HIGH PERF MODE5 |
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high sampling speed (greater than 160 MSPS) | |
Bits[2:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | HIGH PERF MODE6 | HIGH PERF MODE7 | 0 | 0 |
Bits[7:4] | Always write '0' |
Bit 3 | HIGH PERF MODE6 |
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high sampling speed (greater than 160 MSPS) | |
Bit 2 | HIGH PERF MODE7 |
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high sampling speed (greater than 160 MSPS) | |
Bits[1:0] | Always write '0' |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | HIGH PERF MODE8 | 0 | 0 | 0 | 0 | LOW SPEED MODE CH B |
Bits[7:6] | Always write '0' |
Bit 5 | HIGH PERF MODE8 |
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high sampling speed (greater than 160 MSPS). | |
Bits[4:1] | Always write '0' |
Bit 0 | LOW SPEED MODE CH B: Channel B low-speed mode enable |
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to '1' before using this bit. 0 = Low-speed mode is disabled for channel B 1 = Low-speed mode is enabled for channel B |