SBAS534E July 2011 – January 2016 ADS4249
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, AVDD | –0.3 | 2.1 | V | |
Supply voltage, DRVDD | –0.3 | 2.1 | V | |
Voltage between AGND and DRGND | –0.3 | 0.3 | V | |
Voltage between AVDD to DRVDD (when AVDD leads DRVDD) | –2.4 | 2.4 | V | |
Voltage between DRVDD to AVDD (when DRVDD leads AVDD) | –2.4 | 2.4 | V | |
Voltage applied to input pins | INP_A, INM_A, INP_B, INM_B | –0.3 | Minimum (1.9, AVDD + 0.3) |
V |
CLKP, CLKM(2) | –0.3 | AVDD + 0.3 | ||
RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3 |
–0.3 | 3.9 | ||
Operating free-air temperature, TA | –40 | 85 | °C | |
Operating junction temperature, TJ | 125 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
SUPPLIES | |||||
Analog supply voltage, AVDD | 1.7 | 1.8 | 1.9 | V | |
Digital supply voltage, DRVDD | 1.7 | 1.8 | 1.9 | V | |
ANALOG INPUTS | |||||
Differential input voltage | 2 | VPP | |||
Input common-mode | VCM ± 0.05 | V | |||
Maximum analog input frequency with 2-VPP input amplitude(1) | 400 | MHz | |||
Maximum analog input frequency with 1-VPP input amplitude(1) | 600 | MHz | |||
CLOCK INPUT | |||||
Input clock sample rate | Low-speed mode enabled(2) | 1 | 80 | MSPS | |
Low-speed mode disabled(2) (by default after reset) | 80 | 250 | |||
Input clock amplitude differential (VCLKP – VCLKM) |
Sine wave, ac-coupled | 0.2 | 1.5 | VPP | |
LVPECL, ac-coupled | 1.6 | ||||
LVDS, ac-coupled | 0.7 | ||||
LVCMOS, single-ended, ac-coupled | 1.5 | ||||
Input clock duty cycle | Low-speed mode disabled | 35% | 50% | 65% | |
Low-speed mode enabled | 40% | 50% | 60% | ||
DIGITAL OUTPUTS | |||||
Maximum external load capacitance from each output pin to DRGND, CLOAD | 5 | pF | |||
Differential load resistance between the LVDS output pairs (LVDS mode), RLOAD | 100 | Ω | |||
Operating free-air temperature, TA | –40 | +85 | °C |
THERMAL METRIC(1) | ADS4249 | UNIT | |
---|---|---|---|
RGC (VQFN) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 23.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 10.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 4.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 4.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.6 | °C/W |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
ANALOG INPUTS | |||||
Differential input voltage range | 2 | VPP | |||
Differential input resistance (at 200 MHz) | 0.75 | kΩ | |||
Differential input capacitance (at 200 MHz) | 3.7 | pF | |||
Analog input bandwidth (with 50-Ω source impedance, and 50-Ω termination) |
550 | MHz | |||
Analog input common-mode current (per input pin of each channel) |
1.5 | µA/MSPS | |||
VCM | Common-mode output voltage | 0.95(2) | V | ||
VCM output current capability | 4 | mA | |||
DC ACCURACY | |||||
Offset error | –15 | 2.5 | 15 | mV | |
Temperature coefficient of offset error | 0.003 | mV/°C | |||
EGREF | Gain error as a result of internal reference inaccuracy alone | –2 | 2 | %FS | |
EGCHAN | Gain error of channel alone | ±0.1 | 1 | %FS | |
Temperature coefficient of EGCHAN | 0.002 | Δ%/°C | |||
POWER SUPPLY | |||||
IAVDD | Analog supply current | 167 | 190 | mA | |
IDRVDD | Output buffer supply current, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz | 144 | 160 | mA | |
IDRVDD | Output buffer supply current, CMOS interface, no load capacitance, fIN = 2.5 MHz(1) | 94 | mA | ||
Analog power | 301 | 342 | mW | ||
Digital power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz | 259 | 288 | mW | ||
Digital power, CMOS interface, 8-pF external load capacitance(1), fIN = 2.5 MHz |
169 | mW | |||
Global power-down | 25 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1) | ||||||
High-level input voltage | All digital inputs support 1.8-V and 3.3-V CMOS logic levels | 1.3 | V | |||
Low-level input voltage | 0.4 | V | ||||
High-level input current | SDATA, SCLK(2) | VHIGH = 1.8 V | 10 | µA | ||
SEN(3) | VHIGH = 1.8 V | 0 | ||||
Low-level input current | SDATA, SCLK | VLOW = 0 V | 0 | µA | ||
SEN | VLOW = 0 V | 10 | ||||
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT) | ||||||
High-level output voltage | DRVDD – 0.1 | DRVDD | V | |||
Low-level output voltage | 0 | 0.1 | V | |||
DIGITAL OUTPUTS, LVDS INTERFACE | ||||||
High-level output differential voltage |
VODH | With an external 100-Ω termination |
270 | 350 | 430 | mV |
Low-level output differential voltage |
VODL | With an external 100-Ω termination |
–430 | –350 | –270 | mV |
Output common-mode voltage | VOCM | 0.9 | 1.05 | 1.25 | V |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
GENERAL | ||||||
tA | Aperture delay | 0.5 | 0.8 | 1.1 | ns | |
Aperture delay matching between the two channels of the same device | ±70 | ps | ||||
Variation of aperture delay between two devices at the same temperature and DRVDD supply | ±150 | ps | ||||
tJ | Aperture jitter | 140 | fS rms | |||
Wakeup time | Time to valid data after coming out of STANDBY mode | 50 | 100 | µs | ||
Time to valid data after coming out of GLOBAL power-down mode | 100 | 500 | ||||
ADC latency(4) | Default latency after reset | 16 | Clock cycles | |||
Digital functions enabled (EN DIGITAL = 1) | 24 | |||||
DDR LVDS MODE(2) | ||||||
tSU | Data setup time: data valid(3) to zero-crossing of CLKOUTP | 0.6 | 0.88 | ns | ||
tH | Data hold time: zero-crossing of CLKOUTP to data becoming invalid(3) | 0.33 | 0.55 | ns | ||
tPDI | Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over | 5 | 6 | 7.5 | ns | |
LVDS bit clock duty cycle of differential clock, (CLKOUTP-CLKOUTM) | 48% | |||||
tRISE, tFALL |
Data rise time, data fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS |
0.13 | ns | |||
tCLKRISE, tCLKFALL |
Output clock rise time, output clock fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS | 0.13 | ns | |||
PARALLEL CMOS MODE | ||||||
tPDI | Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over | 4.5 | 6.2 | 8.5 | ns | |
Output clock duty cycle of output clock (CLKOUT), 1 MSPS ≤ sampling frequency ≤ 200 MSPS |
50% | |||||
tRISE, tFALL |
Data rise time, data fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 200 MSPS |
0.7 | ns | |||
tCLKRISE, tCLKFALL |
Output clock rise time output clock fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 200 MSPS | 0.7 | ns |
SAMPLING FREQUENCY (MSPS) | SETUP TIME (ns) | HOLD TIME (ns) | tPDI, CLOCK PROPAGATION DELAY (ns) |
||||||
---|---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | |
65 | 5.9 | 6.6 | 0.35 | 0.6 | 5 | 6 | 7.5 | ||
80 | 4.5 | 5.2 | 0.35 | 0.6 | 5 | 6 | 7.5 | ||
125 | 2.3 | 2.9 | 0.35 | 0.6 | 5 | 6 | 7.5 | ||
160 | 1.5 | 2 | 0.33 | 0.55 | 5 | 6 | 7.5 | ||
185 | 1.3 | 1.6 | 0.33 | 0.55 | 5 | 6 | 7.5 | ||
200 | 1.1 | 1.4 | 0.33 | 0.55 | 5 | 6 | 7.5 | ||
230 | 0.76 | 1.06 | 0.33 | 0.55 | 5 | 6 | 7.5 |
SAMPLING FREQUENCY (MSPS) | TIMINGS SPECIFIED WITH RESPECT TO CLKOUT | ||||||||
---|---|---|---|---|---|---|---|---|---|
SETUP TIME(1) (ns) | HOLD TIME(1) (ns) | tPDI, CLOCK PROPAGATION DELAY (ns) |
|||||||
MIN | TYP | MAX | MIN | TYP | MAX | MIN | TYP | MAX | |
65 | 6.1 | 6.7 | 6.7 | 7.5 | 4.5 | 6.2 | 8.5 | ||
80 | 4.7 | 5.2 | 5.3 | 6 | 4.5 | 6.2 | 8.5 | ||
125 | 2.7 | 3.1 | 3.1 | 3.6 | 4.5 | 6.2 | 8.5 | ||
160 | 1.6 | 2.1 | 2.3 | 2.8 | 4.5 | 6.2 | 8.5 | ||
185 | 1.1 | 1.6 | 1.9 | 2.4 | 4.5 | 6.2 | 8.5 | ||
200 | 1 | 1.4 | 1.7 | 2.2 | 4.5 | 6.2 | 8.5 |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency (equal to 1 / tSCLK) | > dc | 20 | MHz | |
tSLOADS | SEN to SCLK setup time | 25 | ns | ||
tSLOADH | SCLK to SEN hold time | 25 | ns | ||
tDSU | SDATA setup time | 25 | ns | ||
tDH | SDATA hold time | 25 | ns |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
t1 | Power-on delay from AVDD and DRVDD power-up to active RESET pulse | 1 | ms | ||
t2 | Reset pulse duration; active RESET signal pulse duration | 10 | ns | ||
1 | µs | ||||
t3 | Register write delay from RESET disable to SEN active | 100 | ns |
NOTE:
A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel interface operation, RESET must be permanently tied high.