8.3.1 Multiplexer

The device contains a very flexible input multiplexer, as shown in Figure 38. Either four single-ended signals, two differential signals, or a combination of two single-ended signals and one differential signal can be measured. The multiplexer is configured by four bits (MUX[3:0]) in the configuration register. When single-ended signals are measured, the negative ADC input (AIN_N) is internally connected to AVSS by a switch within the multiplexer. For system-monitoring purposes, the analog supply (AVDD – AVSS) / 4 or the currently-selected external reference voltage (V_(REFPx) – V_(REFNx)) / 4 can be selected as inputs to the ADC. The multiplexer also offers the possibility to route any of the two programmable current sources to any analog input (AINx) or to any dedicated reference pin (REFP0, REFN0).

Figure 38. Analog Input Multiplexer

Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. To prevent the ESD diodes from turning on, the absolute voltage on any input must stay within the range provided by Equation 4:

If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Overdriving an unused input on the device may affect conversions taking place on other input pins. If any overdrive on unused inputs is possible, TI recommends clamping the signal with external Schottky diodes.

8.3.2 Low-Noise PGA

The device features a low-noise, low-drift, high input impedance, programmable gain amplifier (PGA). The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Three bits (GAIN[2:0]) in the configuration register are used to configure the gain. A simplified diagram of the PGA is shown in Figure 39. The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the PGA gain. The PGA input is equipped with an electromagnetic interference (EMI) filter.

Figure 39. Simplified PGA Diagram

V_IN denotes the differential input voltage V_IN = (V_(AINP) – V_(AINN)). The gain of the PGA can be calculated with Equation 5:

Gain is changed inside the device using a variable resistor, R_G. The differential full-scale input voltage range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 6:

Table 9 shows the corresponding full-scale ranges when using the internal 2.048-V reference.

8.3.2.1 PGA Common-Mode Voltage Requirements

To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are discussed in this section.

The outputs of both amplifiers (A1 and A2) in Figure 39 can not swing closer to the supplies (AVSS and AVDD) than 200 mV. If the outputs OUT_P and OUT_N are driven to within 200 mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition the output voltages must meet Equation 7:

Equation 7. AVSS + 0.2 V ≤ V_(OUTN), V_(OUTP) ≤ AVDD – 0.2 V

Translating the requirements of Equation 7 into requirements referred to the PGA inputs (AIN_P and AIN_N) is beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design, therefore the common-mode voltage at the output of the PGA can be assumed to be the same as the common-mode voltage of the input signal, as shown in Figure 40.

Figure 40. PGA Common-Mode Voltage

The common-mode voltage is calculated using Equation 8:

Equation 8. V_CM = ½ (V_(AINP) + V_(AINN)) = ½ (V_(OUTP) + V_(OUTN))

The voltages at the PGA inputs (AIN_P and AIN_N) can be expressed as Equation 9 and Equation 10:

Equation 9. V_(AINP) = V_CM + ½ V_IN

Equation 10. V_(AINN) = V_CM – ½ V_IN

The output voltages (V_(OUTP) and V_(OUTN)) can then be calculated as Equation 11 and Equation 12:

Equation 11. V_(OUTP) = V_CM + ½ Gain · V_IN

Equation 12. V_(OUTN) = V_CM – ½ Gain · V_IN

The requirements for the output voltages of amplifiers A1 and A2 (Equation 7) can now be translated into requirements for the input common-mode voltage range using Equation 11 and Equation 12, which are given in Equation 13 and Equation 14:

Equation 13. V_{CM (MIN)} ≥ AVSS + 0.2 V + ½ Gain · V_{IN (MAX)}

Equation 14. V_{CM (MAX)} ≤ AVDD – 0.2 V – ½ Gain · V_{IN (MAX)}

In order to calculate the minimum and maximum common-mode voltage limits, the maximum differential input voltage (V_{IN (MAX)}) that occurs in the application must be used. V_{IN (MAX)} can be less than the maximum possible FS value.

In addition to Equation 13, the minimum V_CM must also meet Equation 15 because of the specific design implementation of the PGA.

Equation 15. V_{CM (MIN)} ≥ AVSS + ¼ (AVDD – AVSS)

Figure 41 and Figure 42 show a graphical representation of the common-mode voltage limits for AVDD = 3.3 V and AVSS = 0 V, with gain = 1 and gain = 16, respectively.

AVDD = 3.3 V

Figure 41. Common-Mode Voltage Limits (Gain = 1)

AVDD = 3.3 V

Figure 42. Common-Mode Voltage Limits (Gain = 16)

The following discussion explains how to apply Equation 13 through Equation 15 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference,
V_ref = 2.5 V. The maximum possible differential input voltage V_IN = (V_(AINP) – V_(AINN)) that can be applied is then limited to the full-scale range of FSR = ±2.5 V / 16 = ±0.156 V. Consequently, Equation 13 through Equation 15 yield an allowed V_CM range of 1.45 V ≤ V_CM ≤ 1.85 V.

If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-scale range but is limited to V_{IN (MAX)} = ±0.1 V, for example, then this reduced input signal amplitude relaxes the V_CM restriction to 1.0 V ≤ V_CM ≤ 2.3 V.

In the case of a fully-differential sensor signal, each input (AIN_P, AIN_N) can swing up to ±50 mV around the common-mode voltage (V_(AINP) + V_(AINN)) / 2, which must remain between the limits of 1.0 V and 2.3 V. The output of a symmetrical wheatstone bridge is an example of a fully-differential signal. Figure 43 shows a situation where the common-mode voltage of the input signal is at the lowest limit. V_(OUTN) is exactly at 0.2 V in this case. Any further decrease in common-mode voltage (V_CM) or increase in differential input voltage (V_IN) drives V_(OUTN) below 0.2 V and saturates amplifier A2.

Figure 43. Example where V_CM is at Lowest Limit

In contrast, the signal of an RTD is of a pseudo-differential nature (if implemented as shown in the RTD Measurement section), where the negative input is held at a constant voltage other than 0 V and only the voltage on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this example must be biased at a voltage between 0.95 V and 2.25 V. The positive input can then swing up to
V_{IN (MAX)} = 100 mV above the negative input. Note that in this case the common-mode voltage changes at the same time the voltage on the positive input changes. That is, while the input signal swings between 0 V ≤ V_IN ≤ V_{IN (MAX)}, the common-mode voltage swings between V_(AINN) ≤ V_CM ≤ V_(AINN) + ½ V_{IN (MAX)}. Satisfying the common-mode voltage requirements for the maximum input voltage V_{IN (MAX)} ensures the requirements are met throughout the entire signal range.

Figure 44 and Figure 45 show examples of both fully-differential and pseudo-differential signals, respectively.

Figure 44. Fully-Differential Input Signal

Figure 45. Pseudo-Differential Input Signal

NOTE

Remember, common-mode voltage requirements with PGA enabled (Equation 13 to Equation 15) are as follows:

• V_{CM (MIN)} ≥ AVSS + ¼ (AVDD – AVSS)
• V_{CM (MIN)} ≥ AVSS + 0.2 V + ½ Gain · V_{IN (MAX)}
• V_{CM (MAX)} ≤ AVDD – 0.2 V – ½ Gain · V_{IN (MAX)}

8.3.3 Modulator

A ΔΣ modulator is used in the ADS1120 to convert the analog input voltage into a pulse code modulated (PCM) data stream. The modulator runs at a modulator clock frequency of f_(MOD) = f_(CLK) / 16 in normal and duty-cycle mode and f_(MOD) = f_(CLK) / 8 in turbo mode, where f_(CLK) is either provided by the internal oscillator or the external clock source. Table 10 shows the modulator frequency for each operating mode using either the internal oscillator or an external clock of 4.096 MHz.

8.3.4 Digital Filter

The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the different data rates and always settles within a single cycle. At data rates of 5 SPS and 20 SPS, the filter can be configured to reject 50-Hz or 60-Hz line frequencies or to simultaneously reject 50 Hz and 60 Hz. Two bits (50/60[1:0]) in the configuration register are used to configure the filter accordingly. The frequency responses of the digital filter are shown in Figure 46 to Figure 59 for different output data rates using the internal oscillator or an external 4.096-MHz clock.

The filter notches and output data rate scale proportionally with the clock frequency. For example, a notch that appears at 20 Hz when using a 4.096-MHz clock appears at 10 Hz if a 2.048-MHz clock is used. Note that the internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data rate or conversion time, respectively, and filter notches consequently vary by the same amount. Consider using an external precision clock source if a digital filter notch at a specific frequency with a tighter tolerance is required.

Simultaneous 50-Hz and 60-Hz Rejection, 50/60[1:0] = 01

Figure 46. Filter Response
(DR = 20 SPS)

Simultaneous 50-Hz and 60-Hz Rejection, 50/60[1:0] = 01

Figure 47. Detailed View of Filter Response
(DR = 20 SPS)

50-Hz Rejection Only, 50/60[1:0] = 10

Figure 48. Filter Response
(DR = 20 SPS)

60-Hz Rejection Only, 50/60[1:0] = 11

Figure 50. Filter Response
(DR = 20 SPS)

50/60[1:0] = 00

Figure 52. Filter Response
(DR = 20 SPS)

Figure 54. Filter Response
(DR = 90 SPS)

Figure 56. Filter Response
(DR = 330 SPS)

Figure 58. Filter Response
(DR = 1 kSPS)

50-Hz Rejection Only, 50/60[1:0] = 10

Figure 49. Detailed View of Filter Response
(DR = 20 SPS)

60-Hz Rejection Only, 50/60[1:0] = 11

Figure 51. Detailed View of Filter Response
(DR = 20 SPS)

Figure 53. Filter Response
(DR = 45 SPS)

Figure 55. Filter Response
(DR = 175 SPS)

Figure 57. Filter Response
(DR = 600 SPS)

Figure 59. Filter Response
(DR = 2 kSPS)

8.3.5 Output Data Rate

Table 11 shows the actual conversion times for each data rate setting. The values provided are in terms of t_(CLK) cycles using an external clock with a clock frequency of f_(CLK) = 4.096 MHz. The data rates scale proportionally in case an external clock with a frequency other than 4.096 MHz is used.

Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge. The first conversion starts 210 · t_(CLK) (normal mode, duty-cycle mode) or 114 · t_(CLK) (turbo mode) after the last SCLK falling edge of the START/SYNC command.

Single-shot mode data rates are timed from the last SCLK falling edge of the START/SYNC command to the DRDY falling edge and rounded to the next t_(CLK). In case the internal oscillator is used, an additional oscillator wake-up time of up to 50 µs (normal mode, duty-cycle mode) or 25 µs (turbo mode) must be added in single-shot mode. The internal oscillator starts to power up at the first SCLK rising edge of the START/SYNC command. If an SCLK frequency higher than 160 kHz (normal mode, duty-cycle mode) or 320 kHz (turbo mode) is used, the oscillator may not be fully powered up at the end of the START/SYNC command. The ADC then waits until the internal oscillator is fully powered up before starting a conversion.

Single-shot conversion times in duty-cycle mode are the same as in normal mode. See the Duty-Cycle Mode section for more details on duty-cycle mode operation.

Note that even though the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this discrepancy does not affect the 50-Hz or 60-Hz rejection. To achieve the 50-Hz and 60-Hz rejection specified in the Electrical Characteristics, the external clock frequency must be 4.096 MHz. When using the internal oscillator, the conversion time and filter notches vary by the amount specified in the Electrical Characteristics table for oscillator accuracy.

8.3.6 Voltage Reference

The device offers an integrated low-drift, 2.048-V reference. For applications that require a different reference voltage value or a ratiometric measurement approach, the device offers two differential reference input pairs (REFP0, REFN0 and REFP1, REFN1). In addition, the analog supply (AVDD – AVSS) can be used as a reference.

The reference source is selected by two bits (VREF[1:0]) in the configuration register. By default, the internal reference is selected. The internal voltage reference requires less than 25 µs to fully settle after power-up, when coming out of power-down mode, or when switching from an external reference source to the internal reference.

The differential reference inputs allow freedom in the reference common-mode voltage. REFP0 and REFN0 are dedicated reference inputs whereas REFP1 and REFN1 are shared with inputs AIN0 and AIN3, respectively. All reference inputs are internally buffered to increase input impedance. Therefore, additional reference buffers are usually not required when using an external reference. When used in ratiometric applications, the reference inputs do not load the external circuitry. Note that the analog supply current increases when using an external reference because the reference buffers are enabled.

In most cases the conversion result is directly proportional to the stability of the reference source. Any noise and drift of the voltage reference is reflected in the conversion result.

8.3.7 Clock Source

The device system clock can either be provided by the internal low-drift oscillator or by an external clock source on the CLK input. Connect the CLK pin to DGND before power-up or reset to activate the internal oscillator. Connecting an external clock to the CLK pin at any time deactivates the internal oscillator after two rising edges on the CLK pin are detected. The device then operates on the external clock. After the ADS1120 switches to the external clock, the device can only be switched back to the internal oscillator by cycling the power supplies or by sending a RESET command.

8.3.8 Excitation Current Sources

The device provides two matched programmable excitation current sources (IDACs) for RTD applications. The output current of the current sources can be programmed to 50 μA, 100 μA, 250 μA, 500 μA, 1000 μA, or 1500 μA using the respective bits (IDAC[2:0]) in the configuration register. Each current source can be connected to any of the analog inputs (AINx) as well as to any of the dedicated reference inputs (REFP0 and REFN0). Both current sources can also be connected to the same pin. Routing of the IDACs is configured by bits (I1MUX[2:0], I2MUX[2:0]) in the configuration register. Care must be taken not to exceed the compliance voltage of the IDACs. In other words, limit the voltage on the pin where the IDAC is routed to ≤ (AVDD – 0.9 V), otherwise the specified accuracy of the IDAC current is not met. For three-wire RTD applications, the matched current sources can be used to cancel errors caused by sensor lead resistance (see the 3-Wire RTD Measurement section for more details).

The IDACs require up to 200 µs to start up after the IDAC current is programmed to the respective value using bits IDAC[2:0]. If configuration registers 2 and 3 are not written during the same WREG command, TI recommends to first set the IDAC current to the respective value using bits IDAC[2:0] and thereafter select the routing for each IDAC (I1MUX[2:0], I2MUX[2:0]).

In single-shot mode, the IDACs remain active between any two conversions if the IDAC[2:0] bits are set to a value other than 000. However, the IDACs are powered down whenever the POWERDOWN command is issued.

Note that the analog supply current increases when enabling the IDACs (that is, when the IDAC[2:0] bits are set to a value other than 000). The IDAC circuit needs this bias current to operate even when the IDACs are not routed to any pin (I1MUX[2:0] = I2MUX[2:0] = 000). In addition, the selected output current is drawn from the analog supply when I1MUX[2:0] or I2MUX[2:0] are set to a value other than 000.

8.3.9 Low-Side Power Switch

A low-side power switch with low on-resistance connected between the analog input AIN3/REFN1 and AVSS is integrated in the device as well. This power switch can be used to reduce system power consumption in bridge sensor applications by powering down the bridge circuit between conversions. When the respective bit (PSW) in the configuration register is set, the switch automatically closes when the START/SYNC command is sent and opens when the POWERDOWN command is issued. Note that the switch stays closed between conversions in single-shot mode in case the PSW bit is set to 1. The switch can be opened at any time by setting the PSW bit to 0. By default, the switch is always open.

8.3.10 Sensor Detection

To help detect a possible sensor malfunction, the device provides internal 10-µA, burn-out current sources. When enabled by setting the respective bit (BCS) in the configuration register, one current source sources current to the positive analog input (AIN_P) currently selected while the other current source sinks current form the selected negative analog input (AIN_N).

In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading may also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading may indicate a shorted sensor. Note that the absolute value of the burn-out current sources typically varies by ±10% and the internal multiplexer adds a small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero.

Keep in mind that ADC readings of a functional sensor may be corrupted when the burn-out current sources are enabled. TI recommends disabling the burn-out current sources when preforming the precision measurement, and only enabling them to test for sensor fault conditions.

8.3.11 System Monitor

The device provides some means for monitoring the analog power supply and the external voltage reference. To select a monitoring voltage, the internal multiplexer (MUX[3:0]) must be configured accordingly in the configuration register. The device automatically bypasses the PGA and sets the gain to 1, irrespective of the configuration register settings while the monitoring feature is used. Note that the system monitor function only provides a coarse result and is not meant to be a precision measurement.

When measuring the analog power supply (MUX[3:0] = 1101), the resulting conversion is approximately (AVDD – AVSS) / 4. The device uses the internal 2.048-V reference for the measurement regardless of what reference source is selected in the configuration register (VREF[1:0]).

When monitoring one of the two possible external reference voltage sources (MUX[3:0] = 1100), the result is approximately (V_(REFPx) – V_(REFNx)) / 4. REFPx and REFNx denote the external reference input pair selected in the configuration register (VREF[1:0]). The device automatically uses the internal reference for the measurement.

8.3.12 Offset Calibration

The internal multiplexer offers the option to short both PGA inputs (AIN_P and AIN_N) to mid-supply (AVDD + AVSS) / 2. This option can be used to measure and calibrate the device offset voltage by storing the result of the shorted input voltage reading in a microcontroller and consequently subtracting the result from each following reading. TI recommends taking multiple readings with the inputs shorted and averaging the result to reduce the effect of noise.

8.3.13 Temperature Sensor

The ADS1120 offers an integrated precision temperature sensor. The temperature sensor mode is enabled by setting bit TS = 1 in the configuration register. When in temperature sensor mode, the settings of configuration register 0 have no effect and the device uses the internal reference for measurement, regardless of the selected voltage reference source. Temperature readings follow the same process as the analog inputs for starting and reading conversion results. Temperature data are represented as a 14-bit result that is left-justified within the 16-bit conversion result. Data are output starting with the most significant byte (MSB). When reading the two data bytes, the first 14 bits are used to indicate the temperature measurement result. One 14-bit LSB equals 0.03125°C. Negative numbers are represented in binary twos complement format, as shown in Table 12.

8.4.1 Power-Up and Reset

When the device powers up, a reset is performed. The reset process takes approximately 50 µs. After this power-up reset time, all internal circuitry (including the voltage reference) are stable and communication with the device is possible. As part of the reset process, the device sets all bits in the configuration registers to the respective default settings. By default, the device is set to single-shot mode. After power-up, the device performs a single conversion using the default register settings and then enters a low-power state. When the conversion is complete, the DRDY pin transitions from high to low. The high-to-low transition of the DRDY pin can be used to signal that the ADS1120 is operational and ready to use. The power-up behavior is intended to prevent systems with tight power-supply requirements from encountering a current surge during power-up.

8.4.2 Conversion Modes

The device can be operated in one of two conversion modes that can be selected by the CM bit in the configuration register. These conversion modes are single-shot and continuous conversion mode.

8.4.3 Operating Modes

In addition to the different conversion modes, the device can also be operated in different operating modes that can be selected to trade-off power consumption, noise performance, and output data rate. These modes are: normal mode, duty-cycle mode, turbo mode, and power-down mode.

8.5.1 Serial Interface

The SPI-compatible serial interface of the device is used to read conversion data, read and write the device configuration registers, and control device operation. Only SPI mode 1 (CPOL = 0, CPHA = 1) is supported. The interface consists of five control lines (CS, SCLK, DIN, DOUT/DRDY, and DRDY) but can be used with only four or even three control signals as well. The dedicated data-ready signal (DRDY) can be configured to be shared with DOUT/DRDY. If the serial bus is not shared with any other device, CS can be tied low permanently so that only signals SCLK, DIN, and DOUT/DRDY are required to communicate with the device.

8.5.2 Data Format

The device provides 16 bits of data in binary twos complement format. The size of one code (LSB) is calculated using Equation 16.

A positive full-scale input [V_IN ≥ (+FS – 1 LSB) = (V_ref / Gain – 1 LSB)] produces an output code of 7FFFh and a negative full-scale input (V_IN ≤ –FS = –V_ref / Gain) produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale.

Table 13 summarizes the ideal output codes for different input signals.

Mapping of the analog input signal to the output codes is shown in Figure 60.

Figure 60. Code Transition Diagram

8.5.3 Commands

The device offers six different commands to control device operation, as shown in Table 14. Four commands are stand-alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG) and write (WREG) configuration register data from and to the device require additional information as part of the instruction.

8.5.4 Reading Data

Output pins DRDY and DOUT/DRDY (if the DRDYM bit is set high in the configuration register) transition low when new data are ready for retrieval. The conversion data are written to an internal data buffer. Data can be read directly from this buffer on DOUT/DRDY when DRDY falls low without concern of data corruption. An RDATA command does not have to be sent. Data are shifted out on the SCLK rising edges, MSB first, and consist of two bytes of data.

Figure 61 to Figure 63 show the timing diagrams for reading conversion data in continuous conversion mode and single-shot mode when not using the RDATA command.

Figure 61. Continuous Conversion Mode (DRDYM = 0)

Figure 62. Continuous Conversion Mode (DRDYM = 1)

Figure 63. Single-Shot Mode (DRDYM = 0)

Data can also be read at any time without synchronizing to the DRDY signal using the RDATA command. When an RDATA command is issued, the conversion result currently stored in the data buffer is shifted out on DOUT/DRDY on the following SCLK rising edges. Data can be read continuously with the RDATA command as an alternative to monitoring DRDY or DOUT/DRDY. The DRDY pin can be polled after the LSB is clocked out to determine if a new conversion result was loaded. If a new conversion completes during the read operation but data from the previous conversion are read, then DRDY is low. Otherwise, if the most recent result is read, DRDY is high. Figure 64 and Figure 65 illustrate the behavior for both cases.

Figure 64. State of DRDY when a New Conversion Finishes During an RDATA Command

Figure 65. State of DRDY when the Most Recent Conversion Result is Read During an RDATA Command

8.5.5 Sending Commands

The device serial interface is capable of full-duplex operation while reading conversion data when not using the RDATA command. Full-duplex operation means commands are decoded at the same time that conversion data are read. Commands can be sent on any 8-bit data boundary during a data read operation. When a RREG or RDATA command is recognized, the current data read operation is aborted and the conversion data are corrupted, unless the command is sent while the last byte of the conversion result is retrieved. The device starts to output the requested data on DOUT/DRDY at the first SCLK rising edge after the command byte. To read data without interruption, keep DIN low while clocking out data.

A WREG command can be sent without corrupting an ongoing read operation. Figure 66 shows an example for sending a WREG command to write two configuration registers while reading conversion data in continuous conversion mode. After the command is clocked in (after the 32nd SCLK falling edge), the device resets the digital filter and starts converting with the new register settings. The WREG command can be sent on any of the 8-bit boundaries.

Figure 66. Example of Reading Data while Simultaneously Sending a WREG Command

Note that the serial interface does not decode commands while an RDATA or RREG command is executed. That is, all 16 bits of the conversion result must be read after the RDATA command is issued and all requested registers must be read after a RREG command is sent before a new command can be issued.

8.5.6 Interfacing with Multiple Devices

When connecting multiple ADS1120 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the respective device, DOUT/DRDY enters a 3-state mode. Therefore, DOUT/DRDY cannot be used to indicate when new data are available if CS is high, regardless of the DRDYM bit setting in the configuration register. Only the dedicated DRDY pin indicates that new data are available, because the DRDY pin is actively driven even when CS is high.

In some cases the DRDY pin cannot be interfaced to the microcontroller. This scenario can occur if there are insufficient GPIO channels available on the microcontroller or if the serial interface must be galvanically isolated and thus the amount of channels must be limited. Therefore, in order to evaluate when a new conversion of one of the devices is ready, the microcontroller can periodically drop CS to the respective device and poll the state of the DOUT/DRDY pin. When CS goes low, the DOUT/DRDY pin immediately drives either high or low, provided that the DRDYM bit is configured to 1. If the DOUT/DRDY line drives low, when CS is taken low, new data are currently available. If the DOUT/DRDY line drives high, no new data are available. This procedure requires that DOUT/DRDY is high after reading each conversion result and before taking CS high. To make sure DOUT/DRDY is taken high, send 16 additional SCLKs with DIN held low after each data read operation. DOUT/DRDY reads low during the first eight SCLKs after the conversion result is read, and reads high during the following eight SCLKs, as shown in Figure 67. Alternatively, valid data can be retrieved from the device at any time without concern of data corruption by using the RDATA command.

Figure 67. Example of Taking DOUT/DRDY High After Reading a Conversion Result

8.6.1 Configuration Registers

The device has four 8-bit configuration registers that are accessible through the serial interface using the RREG and WREG commands. The configuration registers control how the device operates and can be changed at any time without causing data corruption. After power-up or reset, all registers are set to the default values (which are all 0). All registers retain their values during power-down mode. Table 15 shows the register map of the configuration registers.