SBAS751B October 2017 – October 2018 ADS122C04
PRODUCTION DATA.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
STANDARD-MODE | |||||
fSCL | SCL clock frequency | 0 | 100 | kHz | |
tHD;STA | Hold time, (repeated) START condition.
After this period, the first clock pulse is generated. |
4 | µs | ||
tLOW | Pulse duration, SCL low | 4.7 | µs | ||
tHIGH | Pulse duration, SCL high | 4.0 | µs | ||
tSU;STA | Setup time, repeated START condition | 4.7 | µs | ||
tHD;DAT | Hold time, data | 0 | µs | ||
tSU;DAT | Setup time, data | 250 | ns | ||
tr | Rise time, SCL, SDA | 1000 | ns | ||
tf | Fall time, SCL, SDA | 250 | ns | ||
tSU;STO | Setup time, STOP condition | 4.0 | µs | ||
tBUF | Bus free time, between STOP and START condition | 4.7 | µs | ||
tVD;DAT | Valid time, data | 3.45 | µs | ||
tVD;ACK | Valid time, acknowledge | 3.45 | µs | ||
FAST-MODE | |||||
fSCL | SCL clock frequency | 0 | 400 | kHz | |
tHD;STA | Hold time, (repeated) START condition.
After this period, the first clock pulse is generated. |
0.6 | µs | ||
tLOW | Pulse duration, SCL low | 1.3 | µs | ||
tHIGH | Pulse duration, SCL high | 0.6 | µs | ||
tSU;STA | Setup time, repeated START condition | 0.6 | µs | ||
tHD;DAT | Hold time, data | 0 | µs | ||
tSU;DAT | Setup time, data | 100 | ns | ||
tr | Rise time, SCL, SDA | 20 | 300 | ns | |
tf | Fall time, SCL, SDA | 20 · (DVDD / 5.5 V) | 250 | ns | |
tSU;STO | Setup time, STOP condition | 0.6 | µs | ||
tBUF | Bus free time, between STOP and START condition | 1.3 | µs | ||
tVD;DAT | Valid time, data | 0.9 | µs | ||
tVD;ACK | Valid time, acknowledge | 0.9 | µs | ||
tSP | Pulse width of spikes that must be suppressed by the input filter | 0 | 50 | ns | |
FAST-MODE PLUS | |||||
fSCL | SCL clock frequency | 0 | 1000 | kHz | |
tHD;STA | Hold time, (repeated) START condition.
After this period, the first clock pulse is generated. |
0.26 | µs | ||
tLOW | Pulse duration, SCL low | 0.5 | µs | ||
tHIGH | Pulse duration, SCL high | 0.26 | µs | ||
tSU;STA | Setup time, repeated START condition | 0.26 | µs | ||
tHD;DAT | Hold time, data | 0 | µs | ||
tSU;DAT | Setup time, data | 50 | ns | ||
tr | Rise time, SCL, SDA | 120 | ns | ||
tf | Fall time, SCL, SDA | Pullup resistor = 350 Ω | 20 · (DVDD / 5.5 V) | 120 | ns |
tSU;STO | Setup time, STOP condition | 0.26 | µs | ||
tBUF | Bus free time, between STOP and START condition | 0.5 | µs | ||
tVD;DAT | Valid time, data | 0.45 | µs | ||
tVD;ACK | Valid time, acknowledge | 0.45 | µs | ||
tSP | Pulse duration of spikes that must be suppressed by the input filter | 0 | 50 | ns | |
RESET PIN | |||||
tw(RSL) | Pulse duration, RESET low | 250 | ns | ||
td(RSSTA) | Delay time, START condition after RESET rising edge(2) | 100 | ns | ||
DRDY PIN | |||||
td(DRSTA) | Delay time, START condition after DRDY falling edge | 0 | ns | ||
TIMEOUT | |||||
Timeout(1) | Normal mode | 14000 | tMOD | ||
Turbo mode | 28000 |