The TLA2021, TLA2022, and TLA2024 devices (TLA202x) are easy-to-use, low-power, 12-bit delta-sigma (ΔΣ) analog-to-digital converters (ADCs) targeted for any type of system-monitoring applications (such as supply or battery voltage supervision, current sensing, or temperature measurements). Offered in an ultra-small, leadless, 10-pin X2QFN package, the TLA2021 and TLA2022 are single-channel ADCs while the TLA2024 features a flexible input multiplexer (MUX) with two differential or four single-ended input measurement options.
The TLA202x integrate a voltage reference and oscillator. Additionally, the TLA2022 and TLA2024 include a programmable gain amplifier (PGA) with selectable input ranges from ±256 mV to ±6.144 V, enabling both large- and small-signal measurements.
The TLA202x communicate via an I2C-compatible interface and operate in either continuous or single-shot conversion mode. The devices automatically power down after one conversion in single-shot conversion mode, significantly reducing power consumption during idle periods.
All of these features, along with a wide operating supply voltage range, make the TLA202x suitable for power- and space-constrained, system-monitoring applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLA2021 | X2QFN (10) | 1.50 mm × 2.00 mm |
TLA2022 | ||
TLA2024 |
DATE | REVISION | NOTES |
---|---|---|
November 2017 | * | Initial release. |
PIN | TYPE | DESCRIPTION | ||
---|---|---|---|---|
NAME | TLA2021, TLA2022 |
TLA2024 | ||
ADDR | 1 | 1 | Digital input | I2C slave address select pin. See the I2C Address Selection section for details. |
AIN0 | 4 | 4 | Analog input | Analog input 0(1) |
AIN1 | 5 | 5 | Analog input | Analog input 1(1) |
AIN2 | — | 6 | Analog input | Analog input 2(1) |
AIN3 | — | 7 | Analog input | Analog input 3(1) |
GND | 3 | 3 | Supply | Ground |
NC | 2, 6, 7 | 2 | — | No connect; always leave floating |
SCL | 10 | 10 | Digital input | Serial clock input. Connect to VDD using a pullup resistor. |
SDA | 9 | 9 | Digital I/O | Serial data input and output. Connect to VDD using a pullup resistor. |
VDD | 8 | 8 | Supply | Power supply. Connect a 0.1-µF, power-supply decoupling capacitor to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power-supply voltage | VDD to GND | –0.3 | 7 | V |
Analog input voltage | AIN0, AIN1, AIN2, AIN3 | GND – 0.3 | VDD + 0.3 | |
Digital input voltage | SDA, SCL, ADDR | GND – 0.3 | 7 | |
Input current | Continuous, any pin except power-supply pins | –10 | 10 | mA |
Temperature | Junction, TJ | –40 | 125 | °C |
Storage, Tstg | –60 | 125 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
POWER SUPPLY | |||||
VDD to GND | 2 | 5.5 | V | ||
ANALOG INPUTS(1) | |||||
FSR | Full-scale input voltage range(2)
(VIN = VAINP – VAINN) |
±0.256 | ±6.144 | V | |
V(AINx) | Absolute input voltage | GND | VDD | V | |
DIGITAL INPUTS | |||||
Digital input voltage | GND | 5.5 | V | ||
TEMPERATURE | |||||
TA | Operating ambient temperature | –40 | 85 | °C |
THERMAL METRIC(1) | TLA202x | UNIT | |
---|---|---|---|
RUG (X2QFN) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 245.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 69.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 172.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 8.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 170.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
Common-mode input impedance | FSR = ±6.144 V(1) | 10 | MΩ | |||
FSR = ±4.096 V(1), FSR = ±2.048 V | 6 | |||||
FSR = ±1.024 V | 3 | |||||
FSR = ±0.512 V, FSR = ±0.256 V | 100 | |||||
Differential input impedance | FSR = ±6.144 V(1) | 22 | MΩ | |||
FSR = ±4.096 V(1) | 15 | |||||
FSR = ±2.048 V | 4.9 | |||||
FSR = ±1.024 V | 2.4 | |||||
FSR = ±0.512 V, ±0.256 V | 710 | kΩ | ||||
SYSTEM PERFORMANCE | ||||||
Resolution (no missing codes) | 12 | Bits | ||||
DR | Data rate | 128, 250, 490, 920, 1600, 2400, 3300 | SPS | |||
Data rate variation | All data rates | –10% | 10% | |||
INL | Integral nonlinearity(2) | 1 | LSB | |||
Offset error | ±1 | LSB | ||||
Offset drift | 0.01 | LSB/°C | ||||
Gain error(3) | 0.05% | |||||
Gain drift(3) | 10 | ppm/°C | ||||
PSRR | Power-supply rejection ratio | 85 | dB | |||
CMRR | Common-mode rejection ratio | 90 | dB | |||
DIGITAL INPUT/OUTPUT | ||||||
VIL | Logic input level, low | GND | 0.3 VDD | V | ||
VIH | Logic input level, high | 0.7 VDD | 5.5 | V | ||
VOL | Logic output level, low | IOL = 3 mA | GND | 0.15 | 0.4 | V |
Input leakage current | GND < VDigital Input < VDD | –10 | 10 | µA | ||
POWER SUPPLY | ||||||
IVDD | Supply current | Power-down | 0.5 | µA | ||
Operating | 150 | |||||
PD | Power dissipation | VDD = 5 V | 0.9 | mW | ||
VDD = 3.3 V | 0.5 | |||||
VDD = 2 V | 0.3 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
STANDARD-MODE | |||||
fSCL | SCL clock frequency | 10 | 100 | kHz | |
tLOW | Pulse duration, SCL low | 4.7 | µs | ||
tHIGH | Pulse duration, SCL high | 4.0 | µs | ||
tHD;STA | Hold time, (repeated) START condition. After this period, the first clock pulse is generated. |
4 | µs | ||
tSU;STA | Setup time, repeated START condition | 4.7 | µs | ||
tHD;DAT | Hold time, data | 0 | µs | ||
tSU;DAT | Setup time, data | 250 | ns | ||
tr | Rise time, SCL, SDA | 1000 | ns | ||
tf | Fall time, SCL, SDA | 250 | ns | ||
tSU;STO | Setup time, STOP condition | 4.0 | µs | ||
tBUF | Bus free time, between STOP and START condition | 4.7 | µs | ||
tVD;DAT | Valid time, data | 3.45 | µs | ||
tVD;ACK | Valid time, acknowledge | 3.45 | µs | ||
FAST-MODE | |||||
fSCL | SCL clock frequency | 10 | 400 | kHz | |
tLOW | Pulse duration, SCL low | 1.3 | µs | ||
tHIGH | Pulse duration, SCL high | 0.6 | µs | ||
tHD;STA | Hold time, (repeated) START condition. After this period, the first clock pulse is generated. |
0.6 | µs | ||
tSU;STA | Setup time, repeated START condition | 0.6 | µs | ||
tHD;DAT | Hold time, data | 0 | µs | ||
tSU;DAT | Setup time, data | 100 | ns | ||
tr | Rise time, SCL, SDA | 20 | 300 | ns | |
tf | Fall time, SCL, SDA | 300 | ns | ||
tSU;STO | Setup time, STOP condition | 0.6 | µs | ||
tBUF | Bus free time, between STOP and START condition | 1.3 | µs | ||
tVD;DAT | Valid time, data | 0.9 | µs | ||
tVD;ACK | Valid time, acknowledge | 0.9 | µs |
The TLA202x are a family of very small, low-power, 12-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The TLA202x consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator, and an I2C interface. The TLA2022 and TLA2024 also integrate a programmable gain amplifier (PGA). Figure 5, Figure 6, and Figure 7 show the functional block diagrams of the TLA2024, TLA2022, and TLA2021, respectively.
The TLA202x ADC core measures a differential signal, VIN, that is the difference of VAINP and VAINN. The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage.
The TLA202x have two available conversion modes: single-shot and continuous-conversion. In single-shot conversion mode, the ADC performs one conversion of the input signal upon request, stores the conversion value to an internal conversion register, and then enters a power-down state. This mode is intended to provide significant power savings in systems that only require periodic conversions or when there are long idle periods between conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is complete. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recently completed conversion.
Figure 8 shows that the TLA2024 contains an analog input multiplexer (MUX). Four single-ended or two differential signals can be measured. Additionally, AIN0 and AIN1 can be measured differentially to AIN3. The multiplexer is configured by bits MUX[2:0] in the configuration register. When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer.
The TLA2021 and TLA2022 do not have an input multiplexer and can either measure one differential signal or one single-ended signal. For single-ended measurements, connect the AIN1 pin to GND externally. In subsequent sections of this data sheet, AINP refers to AIN0 and AINN refers to AIN1 for the TLA2021 and TLA2022.
Electrostatic discharge (ESD) diodes connected to VDD and GND protect the TLA202x analog inputs. Keep the absolute voltage on any input within the range shown in Equation 1 to prevent the ESD diodes from turning on.
If the voltages on the analog input pins can potentially violate these conditions, use external Schottky diodes and series resistors to limit the input current to safe values (see the Absolute Maximum Ratings table).
The TLA202x use a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AINP and AINN. The frequency at which the input signal is sampled is referred to as the sampling frequency or the modulator frequency (fMOD). The TLA202x have a 1-MHz internal oscillator that is further divided by a factor of 4 to generate fMOD at 250 kHz. The capacitors used in this input stage are small, and to external circuitry, the average loading appears resistive. Figure 9 shows this structure. The capacitor values set the resistance and switching rate. Figure 10 shows the timing for the switches in Figure 9. During the sampling phase, switches S1 are closed. This event charges CA1 to VAINP, CA2 to VAINN, and CB to (VAINP – VAINN). During the discharge phase, S1 is first opened and then S2 is closed. CA1 and CA2 then discharge to approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient current from the source driving the TLA202x analog inputs. The average value of this current can be used to calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE.
The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In Figure 9, the common-mode input impedance is ZCM.
The differential input impedance is measured by applying a differential signal to the AINP and AINN inputs where one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and scales with the full-scale range. In Figure 9, the differential input impedance is ZDIFF.
Consider the typical value of the input impedance. Unless the input source has a low impedance, the TLA202x input impedance may affect the measurement accuracy. For sources with high-output impedance, buffering may be necessary. Active buffers introduce noise, offset, and gain errors. Consider all of these factors in high-accuracy applications.
The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most applications, this input impedance drift is negligible and can be ignored.
A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the TLA2022 and TLA2024. The full-scale range is configured by bits PGA[2:0] in the configuration register and can be set to ±6.144 V, ±4.096 V, ±2.048 V, ±1.024 V, ±0.512 V, or ±0.256 V. Table 1 shows the FSR together with the corresponding LSB size. Equation 2 shows how to calculate the LSB size from the selected full-scale range.
FSR | LSB SIZE |
---|---|
±6.144 V(1) | 3 mV |
±4.096 V(1) | 2 mV |
±2.048 V | 1 mV |
±1.024 V | 0.5 mV |
±0.512 V | 0.25 mV |
±0.256 V | 0.125 mV |
The FSR of the TLA2021 is fixed at ±2.048 V.
Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings table. If a VDD supply voltage greater than 4 V is used, the ±6.144-V full-scale range allows input voltages to extend up to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range) a full-scale ADC output code cannot be obtained. For example, with VDD = 3.3 V and FSR = ±4.096 V, only signals up to VIN = ±3.3 V can be measured. The code range that represents voltages |VIN| > 3.3 V is not used in this case.
The TLA202x have an integrated voltage reference. An external reference cannot be used with these devices. Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included in the gain error and gain drift specifications in the Electrical Characteristics table.
The TLA202x have an integrated oscillator running at 1 MHz. No external clock can be applied to operate these devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally with the oscillator frequency.
The TLA202x offer programmable output data rates. Use the DR[2:0] bits in the configuration register to select output data rates of 128 SPS, 250 SPS, 490 SPS, 920 SPS, 1600 SPS, 2400 SPS, or 3300 SPS.
Conversions in the TLA202x settle within a single cycle, which means the conversion time equals 1 / DR.
The TLA202x reset on power-up and set all bits in the configuration register to the respective default settings. The TLA202x enter a power-down state after completion of the reset process. The device interface and digital blocks are active, but no data conversions are performed. The initial power-down state of the TLA202x relieves systems with tight power-supply requirements from encountering a surge during power-up.
The TLA202x respond to the I2C general-call reset command. When the TLA202x receive a general-call reset command (06h), an internal reset is performed as if the device is powered up.
The TLA202x operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the configuration register selects the respective operating mode.
When the MODE bit in the configuration register is set to 1, the TLA202x enter a power-down state, and operate in single-shot conversion mode. This power-down state is the default state for the TLA202x when power is first applied. Although powered down, the devices respond to commands. The TLA202x remain in this power-down state until a 1 is written to the operational status (OS) bit in the configuration register. When the OS bit is asserted, the device powers up in approximately 25 µs, resets the OS bit to 0, and starts a single conversion. When conversion data are ready for retrieval, the OS bit is set to 1 and the device powers down again. Writing a 1 to the OS bit while a conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0 to the MODE bit in the configuration register.
In continuous-conversion mode (MODE bit set to 0), the TLA202x perform conversions continuously. When a conversion is complete, the TLA202x place the result in the conversion data register and immediately begin another conversion. When writing new configuration settings, the currently ongoing conversion completes with the previous configuration settings. Thereafter, continuous conversions with the new configuration settings start. To switch to single-shot conversion mode, write a 1 to the MODE bit in the configuration register or reset the device.
The TLA202x use an I2C-compatible (inter-integrated circuit) interface for serial communication. I2C is a 2-wire, open-drain communication interface that allows communication of a master device with multiple slave devices on the same bus through the use of device addressing. Each slave device on an I2C bus must have a unique address. Communication on the I2C bus always takes place between two devices: one acting as the master and the other as the slave. Both the master and slave can receive and transmit data, but the slave can only read or write under the direction of the master. The TLA202x always act as I2C slave devices.
An I2C bus consists of two lines: SDA and SCL. SDA carries data and SCL provides the clock. Devices on the I2C bus drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors; thus, the bus wires are always high when a device is not driving the lines low. As a result of this configuration, two devices do not conflict. If two devices drive the bus simultaneously, there is no driver contention.
See the I2C-Bus Specification and User Manual from NXP Semiconductors™ for more details.
The TLA202x have one address pin (ADDR) that configures the I2C address of the device. The ADDR pin can connect to GND, VDD, or SCL (as shown in Table 2), which allows three different addresses to be selected with one pin. At the start of every transaction, that is between the START condition (first falling edge of SDA) and the first falling SCL edge of the address byte, the TLA202x decode its address configuration again.
ADDR PIN CONNECTION | SLAVE ADDRESS |
---|---|
GND | 1001 000 |
VDD | 1001 001 |
SCL | 1001 011 |
The TLA202x support I2C interface speeds up to 400 kbit/s. Standard-mode (Sm) with bit rates up to 100 kbit/s, and fast-mode (Fm) with bit rates up to 400 kbit/s are supported. Fast-mode plus (Fm+) and high-speed mode (Hs-mode) are not supported.
The serial clock (SCL) line is used to clock data in and out of the device. The master always drives the clock line. The TLA202x cannot act as a master and as a result can never drive SCL.
The serial data (SDA) line allows for bidirectional communication between the host (the master) and the TLA202x (the slave). When the master reads from a TLA202x, the TLA202x drives the data line; when the master writes to a TLA202x, the master drives the data line.
Data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the SCL line is low. One clock pulse is generated for each data bit transferred. When in an idle state, the master should hold SCL high.
Figure 11 shows the format of the data transfer. The master initiates all transactions with the TLA202x by generating a START (S) condition. A high-to-low transition on the SDA line while SCL is high defines a START condition. The bus is considered to be busy after the START condition.
Following the START condition, the master sends the 7-bit slave address corresponding to the address of the TLA202x that the master wants to communicate with. The master then sends an eighth bit that is a data direction bit (R/W). An R/W bit of 0 indicates a write operation, and an R/W bit of 1 indicates a read operation. After the R/W bit, the master generates a ninth SCLK pulse and releases the SDA line to allow the TLA202x to acknowledge (ACK) the reception of the slave address by pulling SDA low. In case the device does not recognize the slave address, the TLA202x holds SDA high to indicate a not acknowledge (NACK) signal.
Next follows the data transmission. If the transaction is a read (R/W = 1), the TLA202x outputs data on SDA. If the transaction is a write (R/W = 0), the host outputs data on SDA. Data are transferred byte-wise, most significant bit (MSB) first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be acknowledged (via the ACK bit) by the receiver. If the transaction is a read, the master issues the ACK. If the transaction is a write, the TLA202x issues the ACK.
The master terminates all transactions by generating a STOP (P) condition. A low-to-high transition on the SDA line while SCL is high defines a STOP condition. The bus is considered free again tBUF (bus-free time) after the STOP condition.
The TLA202x offer a I2C timeout feature that can be used to recover communication when a serial interface transmission is interrupted. If the host initiates contact with the TLA202x but subsequently remains idle for 25 ms before completing a command, the TLA202x interface is reset. If the TLA202x interface resets because of a timeout condition, the host must abort the transaction and restart the communication again by issuing a new START condition.
The TLA202x respond to the I2C general-call address (0000 000) if the R/W bit is 0. The devices acknowledge the general-call address and, if the next byte is 06h, the TLA202x reset the internal registers and enter a power-down state.
The host can read the conversion data register from the TLA202x, or read and write the configuration register from and to the TLA202x, respectively. The value of the register pointer (RP), which is the first data byte after the slave address of a write transaction (R/W = 0), determines the register that is addressed. Table 3 shows the mapping between the register pointer value and the register that is addressed.
Register data are sent with the most significant byte first, followed by the least significant byte. Within each byte, data are transmitted most significant bit first.
REGISTER POINTER (Hex) | REGISTER |
---|---|
00h | Conversion data register |
01h | Configuration register |
Read the conversion data register or configuration register as shown in Figure 12 by using two I2C communication frames. The first frame is an I2C write operation where the R/W bit at the end of the slave address is 0 to indicate a write. In this frame, the host sends the register pointer that points to the register to read from. The second frame is an I2C read operation where the R/W bit at the end of the slave address is 1 to indicate a read. The TLA202x transmits the contents of the register in this second I2C frame. The master can terminate the transmission after any byte by not acknowledging or issuing a START or STOP condition.
When repeatedly reading the same register, the register pointer does not need to be written every time again because the TLA202x store the value of the register pointer until a write operation modifies the value.
Write the configuration register as shown in Figure 13 using a single I2C communication frame. The R/W bit at the end of the salve address is 0 to indicate a write. The host first sends the register pointer that points to the configuration register, followed by two bytes that represent the register content to write. The TLA202x acknowledge each received byte.
Figure 14 provides a legend for Figure 12 and Figure 13.
The TLA202x provide 12 bits of data in binary two's-complement format that is left-justified within the 16-bit data word. A positive full-scale (+FS) input produces an output code of 7FF0h and a negative full-scale (–FS) input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 4 summarizes the ideal output codes for different input signals. Figure 15 shows code transitions versus input voltage.
INPUT SIGNAL VIN = (VAINP – VAINN) |
IDEAL OUTPUT CODE(1) |
---|---|
≥ +FS (211 – 1) / 211 | 7FF0h |
+FS / 211 | 0010h |
0 | 0000h |
–FS / 211 | FFF0h |
≤ –FS | 8000h |
NOTE
Single-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only use the positive code range from 0000h to 7FF0h. However, because of device offset, the TLA202x can still output negative codes in case VAINP is close to 0 V.
The TLA202x have two registers that are accessible through the I2C interface using the register pointer (RP). The conversion data register contains the result of the last conversion and the configuration register changes the TLA202x operating modes and queries the status of the device. Table 5 lists the access codes for the TLA202x.
Access Type | Code | Description |
---|---|---|
R | R | Read |
R-W | R/W | Read or write |
W | W | Write |
-n | Value after reset or the default value |
The 16-bit conversion data register contains the result of the last conversion in binary two's-complement format. Following power-up, the conversion data register clears to 0, and remains at 0 until the first conversion is complete.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
D3 | D2 | D1 | D0 | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:4 | D[11:0] | R | 000h |
12-bit conversion result |
3:0 | Reserved | R | 0h |
Always reads back 0h |
The 16-bit configuration register controls the operating mode, input selection, data rate, and full-scale range.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
OS | MUX[2:0] | PGA[2:0] | MODE | |||||
R/W-1h | R/W-0h | R/W-2h | R/W-1h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DR[2:0] | RESERVED | |||||||
R/W-4h | R/W-03h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | OS | R/W | 1h |
Operational Status or Single-Shot Conversion Start This bit determines the operational status of the device. OS can only be written when in a power-down state and has no effect when a conversion is ongoing. When writing: 0 : No effect 1 : Start a single conversion (when in a power-down state) When reading: 0 : The device is currently performing a conversion 1 : The device is not currently performing a conversion (default) |
14:12 | MUX[2:0] | R/W | 0h |
Input Multiplexer Configuration (TLA2024 only) These bits configure the input multiplexer. These bits serve no function on the TLA2021 and TLA2022 and are always set to 000. 000 : AINP = AIN0 and AINN = AIN1 (default) 001 : AINP = AIN0 and AINN = AIN3 010 : AINP = AIN1 and AINN = AIN3 011 : AINP = AIN2 and AINN = AIN3 100 : AINP = AIN0 and AINN = GND 101 : AINP = AIN1 and AINN = GND 110 : AINP = AIN2 and AINN = GND 111 : AINP = AIN3 and AINN = GND |
11:9 | PGA[2:0] | R/W | 2h |
Programmable Gain Amplifier Configuration (TLA2022 and TLA2024 Only) These bits set the FSR of the programmable gain amplifier. These bits serve no function on the TLA2021 and are always set to 010. 000 : FSR = ±6.144 V(1) 001 : FSR = ±4.096 V(1) 010 : FSR = ±2.048 V (default) 011 : FSR = ±1.024 V 100 : FSR = ±0.512 V 101 : FSR = ±0.256 V 110 : FSR = ±0.256 V 111 : FSR = ±0.256 V |
8 | MODE | R/W | 1h |
Operating Mode This bit controls the operating mode. 0 : Continuous-conversion mode 1 : Single-shot conversion mode or power-down state (default) |
7:5 | DR[2:0] | R/W | 4h |
Data Rate These bits control the data rate setting. 000 : DR = 128 SPS 001 : DR = 250 SPS 010 : DR = 490 SPS 011 : DR = 920 SPS 100 : DR = 1600 SPS (default) 101 : DR = 2400 SPS 110 : DR = 3300 SPS 111 : DR = 3300 SPS |
4:0 | Reserved | R/W | 03h | Always write 03h |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The following sections give example circuits and suggestions for using the TLA202x in various applications.
Figure 18 shows the principle I2C connections for the TLA202x.
The TLA202x interface directly to standard-mode or fast-mode I2C controllers. Any microcontroller I2C peripheral, including master-only and single-master I2C peripherals, operates with the TLA202x. The TLA202x do not perform clock-stretching (that is, the devices never pull the clock line low), so this function does not need to be provided for unless other clock-stretching devices are present on the same I2C bus.
Pullup resistors are required on both the SDA and SCL lines because I2C bus drivers are open-drain. The size of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors yield lower power consumption when the bus lines are pulled low, but increase the transition times on the bus, which limits the bus speed. Lower-value resistors allow higher interface speeds, but at the expense of higher power consumption when the bus lines are pulled low. Long bus lines have higher capacitance and require smaller pullup resistors to compensate. Do not use resistors that are too small because the bus drivers may be unable to pull the bus lines low.
See the I2C-Bus Specification and User Manual from NXP Semiconductors for more details on pullup resistor sizing.
Up to three TLA202x devices can be connected to a single I2C bus by using different address pin configurations for each device. Use the address pin to set the TLA202x to one of three different I2C addresses. Figure 19 shows an example with three TLA202x devices on the same I2C bus. One set of pullup resistors is required per bus line. The pullup resistor values may need to decrease to compensate for the additional bus capacitance presented by multiple devices and increased line length.
NOTE:
The TLA202x power and input connections are omitted for clarity. The ADDR pin selects the I2C address.The TLA2021 and TLA2022 can measure one single-ended signal, and the TLA2024 up to four single-ended signals. To measure single-ended signals with the TLA2021 and TLA2022, connect AIN1 to GND externally. The TLA2024 measures single-ended signals by properly configuring the MUX[2:0] bits (settings 100 to 111) in the configuration register. Figure 20 shows a single-ended connection scheme for the TLA2024 highlighted in red (a differential connection scheme is shown in green). The single-ended signal range is from 0 V up to the positive supply or +FS (whichever is lower). Negative voltages cannot be applied to these devices because the TLA202x can only accept positive voltages with respect to ground. Only the code range from 0000h to 7FF0h (or a subset thereof in case +FS > VDD) is used in this case.
The TLA2024 also allows AIN3 to serve as a common point for measurements by appropriately setting the MUX[2:0] bits. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the usable voltage and code range, respectively, is increased over the single-ended configuration because negative differential voltages are allowed when GND < V(AIN3) < VDD. Assume the following settings for example: VDD = 5 V, FSR = ±2.048 V, AINP = AIN0, and AINN = AIN3 = 2.5 V. In this case, the voltage at AIN0 can swing from V(AIN0) = 2.5 V – 2.048 V to 2.5 V + 2.048 V using the entire full-scale range.
Analog input filtering serves two purposes:
In most cases, a first-order resistor capacitor (RC) filter is sufficient to completely eliminate aliasing or to reduce the effect of aliasing to a level within the noise floor of the sensor. A good starting point for a system design with the TLA202x is to use a differential RC filter with a cutoff frequency set somewhere between the selected output data rate and 25 kHz. Make the series resistor values as small as possible to reduce voltage drops across the resistors caused by the device input currents to a minimum. However, the resistors should be large enough to limit the current into the analog inputs to less than 10 mA in the event of an overvoltage. Then choose the differential capacitor value to achieve the target filter cutoff frequency. Common-mode filter capacitors to GND can be added as well, but should always be at least ten times smaller than the differential filter capacitor.
Figure 20 shows an example of filtering a differential signal (AIN0, AIN1), and a single-ended signal (AIN3). Equation 3 and Equation 4 show how to calculate the filter cutoff frequencies (fCO) in the differential and single-ended cases, respectively.
For applications where power consumption is critical, the TLA202x support duty cycling that yield significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an TLA202x in power-down state with a data rate set to 3300 SPS can be operated by a microcontroller that instructs a single-shot conversion every 7.81 ms (128 SPS). A conversion at 3300 SPS requires approximately 0.3 ms, so the TLA202x enters power-down state for the remaining 7.51 ms. In this configuration, the TLA202x consume approximately 1/25th the power that is otherwise consumed in continuous-conversion mode. The duty cycling rate is arbitrary and is defined by the master controller.
This section provides an example of an I2C communication sequence between a microcontroller (the master) and a TLA2024 (the slave) configured with a slave address of 1001 000 to start a single-shot conversion and subsequently read the conversion result.
Alternatively, poll the OS bit for a 1 as shown in Figure 22 to determine when the conversion result is ready for retrieval. This option does not work in continuous-conversion mode because the OS bit always reads 0.
To save time, a new conversion can also be started (step 4) before reading the conversion result (step 3). Figure 24 lists a legend for Figure 21 to Figure 23.
This application example describes how to use the TLA2024 to monitor two different supply voltage rails in a system. Figure 25 shows a typical implementation for monitoring two supply voltage rails.
Table 8 lists the design requirements for this application.
DESIGN PARAMETER | VALUE |
---|---|
Device supply voltage | 3.3 V |
Voltage rails to monitor | 1.8 V, 3.3 V |
Measurement accuracy | ±0.5% |
Update rate | 1 ms per rail |
The analog inputs, AIN0 and AIN3, connect directly to the supply voltage rails that are monitored through RC filter resistors. Small filter resistor values of 100 Ω are chosen to reduce voltage drops, and therefore offset errors, caused by the input currents of the TLA2024 to a minimum. Filter capacitors of 0.47 µF are chosen to set the filter cutoff frequencies at 3.39 kHz. In order to get one reading from each of the two supplies within 2 ms, a data rate of 2400 SPS is selected. The device is set up for single-ended measurements using MUX[2:0] settings 100 and 101. A FSR = ±4.096 V is selected to measure the 3.3-V rail. The same FSR can also be used to measure the 1.8-V rail or the FSR can be set to FSR = ±2.048 V.
The measurement results in Figure 26 show that the two supplies can be measured with ±0.5% accuracy over the complete operating ambient temperature range without any offset or gain calibration.
The device requires a single unipolar supply (VDD) to power the analog and digital circuitry of the device.
Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up reset process to complete.
Good power-supply decoupling is important to achieve optimum performance. As shown in Figure 27, VDD must be decoupled with at least a 0.1-µF capacitor to GND. The 0.1-µF bypass capacitor supplies the momentary bursts of extra current required from the supply when the device is converting. Place the bypass capacitor as close to the power-supply pin of the device as possible using low-impedance connections. Use multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoid using vias to connect the capacitors to the device pins for better noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes.
Employ best design practices when laying out a printed-circuit board (PCB) for both analog and digital components. For optimal performance, separate the analog components such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs from digital components such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators. Figure 28 shows an example of good component placement. Although Figure 28 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component.
The following points outline some basic recommendations for the layout of the TLA202x to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout.
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