POWER REQUIREMENTS |
AVDD and IOVDD Supply Current (HART Mode) |
Demodulator active |
External clock, –40°C to +85°C |
|
110 |
150 |
µA |
External clock, –55°C to +105℃ |
|
|
220 |
µA |
External clock, –40°C to +85°C, external reference |
|
100 |
140 |
µA |
External clock, –55°C to +105℃, external reference |
|
|
210 |
µA |
Modulator active |
External clock, –40°C to +85°C |
|
160 |
180 |
µA |
External clock, –55°C to +105℃ |
|
|
250 |
µA |
External clock, –40°C to +85°C, external reference |
|
150 |
170 |
µA |
External clock, –55°C to +105℃, external reference |
|
|
240 |
µA |
Crystal oscillator |
External crystal, 16 pF at XTAL1 and XTAL2 |
|
40 |
65 |
µA |
External crystal, 36 pF at XTAL1 and XTAL2 |
|
40 |
65 |
µA |
Internal oscillator |
External reference |
|
105 |
180 |
µA |
SPI interface |
Additional quiescent current required when interfacing via SPI (DAC8741H only) |
|
5 |
|
µA |
AVDD and IOVDD Supply Current (FF/PA Mode) |
Decoder active |
External clock, –40°C to +85°C |
|
160 |
220 |
µA |
External clock, –55°C to +105℃ |
|
|
330 |
µA |
External clock, –40°C to +85°C, external reference |
|
175 |
200 |
µA |
External clock, –55°C to +105℃, external reference |
|
|
320 |
µA |
Encoder active |
External clock, –40°C to +85°C |
|
175 |
250 |
µA |
External clock, –55°C to +105℃ |
|
|
360 |
µA |
External clock, –40°C to +85°C, external reference |
|
165 |
235 |
µA |
External clock, –55°C to +105℃, external reference |
|
|
350 |
µA |
Crystal oscillator |
External crystal, 16 pF at XTAL1 and XTAL2 |
|
40 |
65 |
µA |
External crystal, 36 pF at XTAL1 and XTAL2 |
|
40 |
65 |
µA |
SPI interface |
Additional quiescent current required when interfacing via SPI (DAC8741H) |
|
5 |
|
µA |
AVDD and IOVDD Supply Current (All Modes) |
Power-down mode |
Internal reference disabled, –40°C to +85°C, no active clock input |
|
30 |
60 |
µA |
Internal reference disabled, –55°C to +105℃, no active clock input |
|
|
182 |
µA |
CLOCK REQUIREMENTS |
EXTERNAL CLOCK (HART MODE) |
External clock source frequency |
3.6864-MHz clock |
3.6469 |
3.6864 |
3.7232 |
MHz |
1.2288-MHz clock |
1.2165 |
1.2288 |
1.2411 |
MHz |
EXTERNAL CLOCK (FF/PA MODE) |
External clock source frequency |
4-MHz clock |
3.96 |
4 |
4.04 |
MHz |
INTERNAL OSCILLATOR |
Frequency |
–40°C to +105℃ |
1.2165 |
1.2288 |
1.2411 |
MHz |
VOLTAGE REFERENCE |
INTERNAL REFERENCE VOLTAGE |
Internal reference voltage |
|
1.47 |
1.5 |
1.53 |
V |
Load regulation |
|
|
1.3 |
|
V/mA |
Capacitive load |
Specified by design |
|
1 |
|
µF |
OPTIONAL EXTERNAL REFERENCE VOLTAGE |
External reference input voltage |
|
2.375 |
2.5 |
2.625 |
V |
External reference input current |
Demodulator |
|
4.5 |
|
µA |
Modulator |
|
4.5 |
|
µA |
Internal oscillator |
|
4.5 |
|
µA |
Power-down |
|
4.5 |
|
µA |
HART MODEM |
MOD_IN INPUT (HART MODE) |
Input voltage range |
External reference source, specified by design. Signal applied at the input to the dc blocking capacitor. |
0 |
|
1.5 |
VPP |
Internal reference source, specified by design. Signal applied at the input to the dc blocking capacitor. |
0 |
|
1.5 |
VPP |
Receiver sensitivity |
Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. |
80 |
100 |
120 |
mVPP |
MOD_OUT OUTPUT (HART MODE) |
Output voltage |
AC-coupled (2.2 µF), measured at MOD_OUT pin with 160-Ω load |
450 |
460 |
480 |
mVPP |
Mark frequency |
Internal oscillator |
|
1200 |
|
Hz |
Space frequency |
Internal oscillator |
|
2200 |
|
Hz |
Frequency error |
Internal oscillator, –40°C to +105℃ |
-1 |
|
1 |
% |
Phase continuity error |
Specified by design |
|
|
0 |
Degrees |
Minimum resistive load |
160-Ω, ac coupled with 2.2 µF, specified by design |
160 |
|
|
Ω |
Transmit impedance |
RTS low, measured at the MOD_OUT pin, 1-mA measurement current |
|
13 |
|
Ω |
RTS high, measured at the MOD_OUT pin, ±200-nA measurement current |
|
250 |
|
kΩ |
FF / PA MODEM |
MOD_IN INPUT (FF/PA MODE) |
Input voltage range |
External reference source, specified by design. Signal applied at the input to the DC blocking capacitor. |
0 |
|
1 |
Vp-p |
Internal reference enabled, specified by design. Signal applied at the input to the DC blocking capacitor. |
0 |
|
1 |
Vp-p |
Receiver jitter tolerance |
Edge-to-edge measurement of Manchester encoded waveforms |
-3.2 |
|
3.2 |
µs |
Receiver sensitivity |
Threshold for successful carrier detection and decoding, assuming ideal Manchester encoded input trapezoidal signals with 6µs rise time, valid preamble byte(s) and start delimiter byte, using internal filter. |
75 |
|
|
mVp-p |
MOD_OUT OUTPUT (FF/PA MODE) |
Output voltage |
|
|
800 |
|
mVp-p |
Maximum amplitude difference |
Maximum difference in positive and negative amplitude signals |
-50 |
|
50 |
mV |
Transmit bit rate |
|
31.1875 |
31.25 |
31.3125 |
kbit/s |
Transmit jitter |
Measured with respect to ideal crossing of high time and low time |
-0.8 |
|
0.8 |
µs |
Output signal distortion |
Measured peak to trough distortion for positive and negative amplitude voltage outputs |
-10 |
|
10 |
% |
Rise and fall time |
10% to 90% of peak to peak signal |
|
|
8 |
µs |
Slew rate |
10% to 90% of peak to peak signal |
|
|
0.2 |
V/µs |
DIGITAL REQUIREMENTS |
DIGITAL INPUTS |
VIH, input high voltage |
|
0.7 x IOVDD |
|
|
V |
VIL, input low voltage |
|
|
|
0.3 x IOVDD |
V |
CLK_CFG0, input high voltage |
Specified by design |
0.8 x IOVDD |
|
|
V |
CLK_CFG0, input mid-scale voltage |
Specified by design |
0.4 x IOVDD |
|
0.55 x IOVDD |
V |
CLK_CFG0, input low voltage |
Specified by design |
|
|
0.15 x IOVDD |
|
Input current |
|
-1 |
|
1 |
µA |
Input capcitance |
|
|
5 |
|
pF |
DIGITAL OUTPUTS |
VOH, output high voltage |
200-µA source or sink |
IOVDD - 0.5 |
|
|
V |
VOL, output low voltage |
200-µA source or sink |
|
|
0.4 |
V |