SBAS856D June   2017  – May 2019 DAC8740H , DAC8741H

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: DAC8740H
    2.     Pin Functions: DAC8741H
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  HART Modulator
      2. 8.3.2  HART Demodulator
      3. 8.3.3  FOUNDATION Fieldbus or PROFIBUS PA Manchester Encoder
      4. 8.3.4  FOUNDATION Fieldbus or PROFIBUS PA Manchester Decoder
      5. 8.3.5  Internal Reference
      6. 8.3.6  Clock Configuration
      7. 8.3.7  Reset and Power-Down
      8. 8.3.8  Full-Duplex Mode
      9. 8.3.9  I/O Selection
      10. 8.3.10 Jabber Inhibitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 UART Interfaced HART
      2. 8.4.2 UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      3. 8.4.3 SPI Interfaced HART
      4. 8.4.4 SPI Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      5. 8.4.5 Digital Interface
        1. 8.4.5.1 UART
          1. 8.4.5.1.1 UART Carrier Detect
        2. 8.4.5.2 SPI
          1. 8.4.5.2.1 SPI Cyclic Redundancy Check
          2. 8.4.5.2.2 SPI Interrupt Request
    5. 8.5 Register Maps
      1. 8.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 9. CONTROL Register Field Descriptions
      2. 8.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 10. RESET Register Field Descriptions
      3. 8.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 11. MODEM_STATUS Register Field Descriptions
      4. 8.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 12. MODEM_IRQ_MASK Register Field Descriptions
      5. 8.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 13. MODEM_CONTROL Register Field Descriptions
      6. 8.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 14. FIFO_D2M Register Field Descriptions
      7. 8.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 15. FIFO_M2D Register Field Descriptions
      8. 8.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 16. FIFO_LEVEL_SET Register Field Descriptions
      9. 8.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 17. PAFF_JABBER Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design Recommendations
      2. 9.1.2 Selecting the Crystal or Resonator
      3. 9.1.3 Included Functions and Filter Selection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DAC8740H HART Modem
        2. 9.2.2.2 2-Wire Current Loop
        3. 9.2.2.3 Regulator
        4. 9.2.2.4 DAC
        5. 9.2.2.5 Amplifiers
        6. 9.2.2.6 Diodes
        7. 9.2.2.7 Passives
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.4.5.2 SPI

The SPI interface can operate on SCLK speeds up to 12.5 MHz, but the frame-rate must be greater than 2442 ns in HART mode and 3000 ns in FOUNDATION Fieldbus and PROFIBUS PA mode. Frames must contain at least 24-bits without CRC enabled and 32-bits with CRC enabled. The data within the frame are right justified, meaning that upon the rising edge of CS the right-most, or last, 24-bits or 32-bits are evaluated as the input data word. Two modes of SPI are supported by the interface: clock polarity 0 and clock phase 1, or clock polarity 1 and clock phase 0.

The SDO pin will output data on the rising edge of SCLK or the falling edge of CS. SDO will always provide information from the previous frame, if the previous frame was a read then the output data will be the requested data. If the previous write was a command or register write, that data will be repeated. This allows a method for the user to verify what was written to the device. If CRC is enabled and write data is being repeated on SDO, the CRC provided during the previous frame will be output – not a newly calculated CRC.

The SPI frame structure is shown in Table 6. The frame includes a read/write bit, followed by a 7-bit address, then 16-bit write data for a write frame or don’t care bits for a read frame. If CRC is enabled, an additional 8-bits are placed at the end of the frame containing the CRC word.

Table 6. SPI Frame Structure

R/W FRAME D23 D22:16 D15:0
Write Frame 0 7-Bit Address Write Data
Read Frame 1 7-Bit Address X