SBAS856D
June 2017 – May 2019
DAC8740H
,
DAC8741H
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions: DAC8740H
Pin Functions: DAC8741H
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
HART Modulator
8.3.2
HART Demodulator
8.3.3
FOUNDATION Fieldbus or PROFIBUS PA Manchester Encoder
8.3.4
FOUNDATION Fieldbus or PROFIBUS PA Manchester Decoder
8.3.5
Internal Reference
8.3.6
Clock Configuration
8.3.7
Reset and Power-Down
8.3.8
Full-Duplex Mode
8.3.9
I/O Selection
8.3.10
Jabber Inhibitor
8.4
Device Functional Modes
8.4.1
UART Interfaced HART
8.4.2
UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA
8.4.3
SPI Interfaced HART
8.4.4
SPI Interfaced FOUNDATION Fieldbus or PROFIBUS PA
8.4.5
Digital Interface
8.4.5.1
UART
8.4.5.1.1
UART Carrier Detect
8.4.5.2
SPI
8.4.5.2.1
SPI Cyclic Redundancy Check
8.4.5.2.2
SPI Interrupt Request
8.5
Register Maps
8.5.1
CONTROL Register (Offset = 2h) [reset = 0x8042]
Table 9.
CONTROL Register Field Descriptions
8.5.2
RESET Register (Offset = 7h) [reset = 0x0000]
Table 10.
RESET Register Field Descriptions
8.5.3
MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
Table 11.
MODEM_STATUS Register Field Descriptions
8.5.4
MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
Table 12.
MODEM_IRQ_MASK Register Field Descriptions
8.5.5
MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
Table 13.
MODEM_CONTROL Register Field Descriptions
8.5.6
FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
Table 14.
FIFO_D2M Register Field Descriptions
8.5.7
FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
Table 15.
FIFO_M2D Register Field Descriptions
8.5.8
FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
Table 16.
FIFO_LEVEL_SET Register Field Descriptions
8.5.9
PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
Table 17.
PAFF_JABBER Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.1.1
Design Recommendations
9.1.2
Selecting the Crystal or Resonator
9.1.3
Included Functions and Filter Selection
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
DAC8740H HART Modem
9.2.2.2
2-Wire Current Loop
9.2.2.3
Regulator
9.2.2.4
DAC
9.2.2.5
Amplifiers
9.2.2.6
Diodes
9.2.2.7
Passives
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Related Links
12.3
Receiving Notification of Documentation Updates
12.4
Community Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
7.7
Typical Characteristics
Figure 2.
HART Mode External Band-Pass Filter Response
Figure 4.
FF / PA Mode External Band-Pass Filter Response
Figure 6.
Internal Reference Voltage vs AVDD
Figure 8.
HART TX Carrier Start Time
Figure 10.
HART RX Carrier Detect Off Timing
Figure 12.
HART Mode IOVDD Supply Current vs Voltage With External Reference
Figure 14.
HART Mode IOVDD Supply Current vs Voltage With Internal Reference
Figure 16.
FF / PA Mode IOVDD Supply Current vs Voltage With External Reference
Figure 18.
FF / PA Mode IOVDD Supply Current vs Voltage With Internal Reference
Figure 20.
Typical Manchester Encoded Trapezoid, No Filter
Figure 22.
MOD_OUT Voltage vs R
LOAD
Figure 3.
HART Mode Internal Band-Pass Filter Response
Figure 5.
FF / PA Mode Internal Band-Pass Filter Response
Figure 7.
Internal Reference Voltage vs Temperature
Figure 9.
HART TX Carrier Stop / Decay Time
Figure 11.
HART RX Carrier Detect On Timing
Figure 13.
HART Mode AVDD Supply Current vs Voltage With External Reference
Figure 15.
HART Mode AVDD Supply Current vs Voltage With Internal Reference
Figure 17.
FF / PA Mode AVDD Supply Current vs Voltage With External Reference
Figure 19.
FF / PA Mode AVDD Supply Current vs Voltage With Internal Reference
Figure 21.
Typical Manchester Encoded Trapezoid, With Suggested Filter Response