SBAS856D June   2017  – May 2019 DAC8740H , DAC8741H

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions: DAC8740H
    2.     Pin Functions: DAC8741H
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  HART Modulator
      2. 8.3.2  HART Demodulator
      3. 8.3.3  FOUNDATION Fieldbus or PROFIBUS PA Manchester Encoder
      4. 8.3.4  FOUNDATION Fieldbus or PROFIBUS PA Manchester Decoder
      5. 8.3.5  Internal Reference
      6. 8.3.6  Clock Configuration
      7. 8.3.7  Reset and Power-Down
      8. 8.3.8  Full-Duplex Mode
      9. 8.3.9  I/O Selection
      10. 8.3.10 Jabber Inhibitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 UART Interfaced HART
      2. 8.4.2 UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      3. 8.4.3 SPI Interfaced HART
      4. 8.4.4 SPI Interfaced FOUNDATION Fieldbus or PROFIBUS PA
      5. 8.4.5 Digital Interface
        1. 8.4.5.1 UART
          1. 8.4.5.1.1 UART Carrier Detect
        2. 8.4.5.2 SPI
          1. 8.4.5.2.1 SPI Cyclic Redundancy Check
          2. 8.4.5.2.2 SPI Interrupt Request
    5. 8.5 Register Maps
      1. 8.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 9. CONTROL Register Field Descriptions
      2. 8.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 10. RESET Register Field Descriptions
      3. 8.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 11. MODEM_STATUS Register Field Descriptions
      4. 8.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 12. MODEM_IRQ_MASK Register Field Descriptions
      5. 8.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 13. MODEM_CONTROL Register Field Descriptions
      6. 8.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 14. FIFO_D2M Register Field Descriptions
      7. 8.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 15. FIFO_M2D Register Field Descriptions
      8. 8.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 16. FIFO_LEVEL_SET Register Field Descriptions
      9. 8.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 17. PAFF_JABBER Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design Recommendations
      2. 9.1.2 Selecting the Crystal or Resonator
      3. 9.1.3 Included Functions and Filter Selection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DAC8740H HART Modem
        2. 9.2.2.2 2-Wire Current Loop
        3. 9.2.2.3 Regulator
        4. 9.2.2.4 DAC
        5. 9.2.2.5 Amplifiers
        6. 9.2.2.6 Diodes
        7. 9.2.2.7 Passives
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

UART Interfaced FOUNDATION Fieldbus or PROFIBUS PA

FOUNDATION Fieldbus and PROFIBUS PA are half-duplex communication protocols where only the encoder or decoder are active at any time and the DAC874xH arbitrates over which path is active. When interfacing the FOUNDATION Fieldbus or PROFIBUS PA modem via the UART interface, data placed in the transmit FIFO is automatically placed on the FF/PA bus until the FIFO is empty any time the device is not receiving data, assuming correct data format.

When receiving data the decoder will expect a preamble byte(s) and a start delimiter byte. These bytes, as well as the stop byte, will be stripped from the UART communication and only the first data byte will be transmitted to start the data packet. The host controller must use a timer to detect the end of the packet. Each byte transmitted on the UART will be at 57.6 kHz baud and byte spacing of 256 µs. If a new byte has not been started within 512 µs it can be assumed that the incoming packet has ended.

The device expects to see a four byte sequence to initiate transmission: 0xEA followed by 0x80-0x9F, where bits 4:3 of the second byte configure an interrupt threshold for the transmit FIFO level and bits 2:0 set the number of preamble bytes to be transmitted. The third byte contains the information to configure the Jabber Inhibitor followed by the final byte of 0xAE. To send inverted Manchester encoded data the first byte, 0xEA, is inverted to 0x15 and the first three bits of the second byte are inverted such that the range of values for the second byte are from 0x60-0x7F. The functionality of bits 4:3 and 2:0 and the Jabber Inhibitor byte remain the same and the final byte is inverted to 0x51. The details concerning this four byte sequence are explained in Table 3 to Table 5.

Table 3. B3 and B2 UART Initialization Byte Sequence

B3 B2
Mode D7:D0 D7 D6 D5 D4 D3 D2 D1 D0
Noninverted 1 1 1 0 1 0 1 0 1 0 0 D2M_LEVEL PRE_BYTES
Inverted 0 0 0 1 0 1 0 1 0 1 1 D2M_LEVEL PRE_BYTES

Table 4. B1 and B0 UART Initialization Byte Sequence

B1 B0
Mode D7:D0 D7 D6 D5 D4 D3 D2 D1 D0
Noninverted JABBER_TIMEOUT 1 0 1 0 1 1 1 0
Inverted JABBER_TIMEOUT 0 1 0 1 0 0 0 1

Table 5. B2 Bit-Field Definitions

CONTROL BITS DESCRIPTION
D2M_LEVEL 0 0 Alarm on UART_RTS when transmit FIFO has less than 2 bytes loaded
0 1 Alarm on UART_RTS when transmit FIFO has less than 4 bytes loaded
1 0 Alarm on UART_RTS when transmit FIFO has less than 6 bytes loaded
1 1 Alarm on UART_RTS when transmit FIFO has less than 8 bytes loaded
PRE_BYTES Number of preamble bytes is equivalent to the straight binary decimal value in this register plus one

The JABBER_TIMEOUT bits control the timeout period for the Jabber Inhibitor. If a value of 0x0 is programmed the Jabber Inhibitor is disabled. Otherwise, the timer will be programmed in 2.048 ms increments such that the timeout can be calculated as shown below. If the Jabber Inhibitor triggers the CD pin will be taken high. The CD pin will be returned to logic low when the silence period of 3 seconds has ended.

Equation 1. TimeOut = JABBER_TIMEOUT × 2.048 ms

The encoder begins transmitting data after the following conditions are met: a valid four-byte transmission initiation sequence has been sent to the device, the FIFO is not empty, and the device is not receiving data. Transmission begins by sending the preamble byte or bytes, followed by a start delimiter. Then, the encoder begins to remove data from the FIFO, and creates at least a five-byte lag of the encoder with respect to the UART.

During transmission of a packet, the UART must take care to make sure that the FIFO does not become empty before the packet is complete. The encoder transmits at a baud rate of 31.25 kHz or 256 µs per byte in the FIFO, so the UART must keep up with this rate. The four-byte sequence that initiates a transmission includes setting a transmit FIFO threshold in bits 4:3. When the FIFO level is less than or equal to this threshold, the UART_RTS pin is taken high; this can be leveraged to make sure the FIFO is not prematurely empty. After the FIFO is empty, a stop delimiter is placed on the bus, and a new packet can be initiated with a new four-byte transmission initiation sequence.

The device expects a UART baud rate of 57.6 kHz. This baud rate is faster than the 31.25-kHz baud rate specified by FOUNDATION Fieldbus and PROFIBUS PA; therefore, FIFO overflow is possible. To prevent FIFO overflow, the UART_RTS pin FIFO threshold alarm can be leveraged by never adding more data to the FIFO than the FIFO can contain, based on the programmed alarm threshold.