SBAS868A May   2019  – May 2020 ADS7128

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      ADS7128 Block Diagram and Applications
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1      Absolute Maximum Ratings
    2. 7.2      ESD Ratings
    3. 7.3      Recommended Operating Conditions
    4. 7.4      Thermal Information
    5. 7.5      Electrical Characteristics
    6. Table 1. I2C Timing Requirements
    7. Table 2. Timing Requirements
    8. Table 3. I2C Switching Characteristics
    9. 7.6      Switching Characteristics
    10. 7.7      Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer and ADC
      2. 8.3.2  Reference
      3. 8.3.3  ADC Transfer Function
      4. 8.3.4  ADC Offset Calibration
      5. 8.3.5  I2C Address Selector
      6. 8.3.6  Programmable Averaging Filter
      7. 8.3.7  CRC on Data Interface
      8. 8.3.8  General-Purpose I/Os (GPIOs)
      9. 8.3.9  Oscillator and Timing Control
      10. 8.3.10 Output Data Format
      11. 8.3.11 Digital Window Comparator
        1. 8.3.11.1 Interrupts From Digital Inputs
        2. 8.3.11.2 Changing Digital Outputs on Alert and ZCD
          1. 8.3.11.2.1 Changing Digital Outputs on Alerts
            1. 8.3.11.2.1.1 Trigger
            2. 8.3.11.2.1.2 Output Value
          2. 8.3.11.2.2 Changing Digital Outputs Synchronous to the Zero-Crossing Detect
      12. 8.3.12 Root-Mean-Square Module
      13. 8.3.13 Zero-Crossing-Detect Module
      14. 8.3.14 Minimum, Maximum, and Latest Data Registers
      15. 8.3.15 I2C Protocol Features
        1. 8.3.15.1 General Call
        2. 8.3.15.2 General Call With Software Reset
        3. 8.3.15.3 General Call With a Software Write to the Programmable Part of the Slave Address
        4. 8.3.15.4 Configuring the Device for High-Speed I2C Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Power-Up and Reset
      2. 8.4.2 Manual Mode
      3. 8.4.3 Auto-Sequence Mode
      4. 8.4.4 Autonomous Mode
    5. 8.5 Programming
      1. 8.5.1 Reading Registers
        1. 8.5.1.1 Single Register Read
        2. 8.5.1.2 Reading a Continuous Block of Registers
      2. 8.5.2 Writing Registers
        1. 8.5.2.1 Single Register Write
        2. 8.5.2.2 Set Bit
        3. 8.5.2.3 Clear Bit
        4. 8.5.2.4 Writing a Continuous Block of Registers
    6. 8.6 ADS7128 Registers
      1. 8.6.1   SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
        1. Table 15. SYSTEM_STATUS Register Field Descriptions
      2. 8.6.2   GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
        1. Table 16. GENERAL_CFG Register Field Descriptions
      3. 8.6.3   DATA_CFG Register (Address = 0x2) [reset = 0x0]
        1. Table 17. DATA_CFG Register Field Descriptions
      4. 8.6.4   OSR_CFG Register (Address = 0x3) [reset = 0x0]
        1. Table 18. OSR_CFG Register Field Descriptions
      5. 8.6.5   OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
        1. Table 19. OPMODE_CFG Register Field Descriptions
      6. 8.6.6   PIN_CFG Register (Address = 0x5) [reset = 0x0]
        1. Table 20. PIN_CFG Register Field Descriptions
      7. 8.6.7   GPIO_CFG Register (Address = 0x7) [reset = 0x0]
        1. Table 21. GPIO_CFG Register Field Descriptions
      8. 8.6.8   GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
        1. Table 22. GPO_DRIVE_CFG Register Field Descriptions
      9. 8.6.9   GPO_VALUE Register (Address = 0xB) [reset = 0x0]
        1. Table 23. GPO_VALUE Register Field Descriptions
      10. 8.6.10  GPI_VALUE Register (Address = 0xD) [reset = 0x0]
        1. Table 24. GPI_VALUE Register Field Descriptions
      11. 8.6.11  ZCD_BLANKING_CFG Register (Address = 0xF) [reset = 0x0]
        1. Table 25. ZCD_BLANKING_CFG Register Field Descriptions
      12. 8.6.12  SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
        1. Table 26. SEQUENCE_CFG Register Field Descriptions
      13. 8.6.13  CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
        1. Table 27. CHANNEL_SEL Register Field Descriptions
      14. 8.6.14  AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
        1. Table 28. AUTO_SEQ_CH_SEL Register Field Descriptions
      15. 8.6.15  ALERT_CH_SEL Register (Address = 0x14) [reset = 0x0]
        1. Table 29. ALERT_CH_SEL Register Field Descriptions
      16. 8.6.16  ALERT_MAP Register (Address = 0x16) [reset = 0x0]
        1. Table 30. ALERT_MAP Register Field Descriptions
      17. 8.6.17  ALERT_PIN_CFG Register (Address = 0x17) [reset = 0x0]
        1. Table 31. ALERT_PIN_CFG Register Field Descriptions
      18. 8.6.18  EVENT_FLAG Register (Address = 0x18) [reset = 0x0]
        1. Table 32. EVENT_FLAG Register Field Descriptions
      19. 8.6.19  EVENT_HIGH_FLAG Register (Address = 0x1A) [reset = 0x0]
        1. Table 33. EVENT_HIGH_FLAG Register Field Descriptions
      20. 8.6.20  EVENT_LOW_FLAG Register (Address = 0x1C) [reset = 0x0]
        1. Table 34. EVENT_LOW_FLAG Register Field Descriptions
      21. 8.6.21  EVENT_RGN Register (Address = 0x1E) [reset = 0x0]
        1. Table 35. EVENT_RGN Register Field Descriptions
      22. 8.6.22  HYSTERESIS_CH0 Register (Address = 0x20) [reset = 0xF0]
        1. Table 36. HYSTERESIS_CH0 Register Field Descriptions
      23. 8.6.23  HIGH_TH_CH0 Register (Address = 0x21) [reset = 0xFF]
        1. Table 37. HIGH_TH_CH0 Register Field Descriptions
      24. 8.6.24  EVENT_COUNT_CH0 Register (Address = 0x22) [reset = 0x0]
        1. Table 38. EVENT_COUNT_CH0 Register Field Descriptions
      25. 8.6.25  LOW_TH_CH0 Register (Address = 0x23) [reset = 0x0]
        1. Table 39. LOW_TH_CH0 Register Field Descriptions
      26. 8.6.26  HYSTERESIS_CH1 Register (Address = 0x24) [reset = 0xF0]
        1. Table 40. HYSTERESIS_CH1 Register Field Descriptions
      27. 8.6.27  HIGH_TH_CH1 Register (Address = 0x25) [reset = 0xFF]
        1. Table 41. HIGH_TH_CH1 Register Field Descriptions
      28. 8.6.28  EVENT_COUNT_CH1 Register (Address = 0x26) [reset = 0x0]
        1. Table 42. EVENT_COUNT_CH1 Register Field Descriptions
      29. 8.6.29  LOW_TH_CH1 Register (Address = 0x27) [reset = 0x0]
        1. Table 43. LOW_TH_CH1 Register Field Descriptions
      30. 8.6.30  HYSTERESIS_CH2 Register (Address = 0x28) [reset = 0xF0]
        1. Table 44. HYSTERESIS_CH2 Register Field Descriptions
      31. 8.6.31  HIGH_TH_CH2 Register (Address = 0x29) [reset = 0xFF]
        1. Table 45. HIGH_TH_CH2 Register Field Descriptions
      32. 8.6.32  EVENT_COUNT_CH2 Register (Address = 0x2A) [reset = 0x0]
        1. Table 46. EVENT_COUNT_CH2 Register Field Descriptions
      33. 8.6.33  LOW_TH_CH2 Register (Address = 0x2B) [reset = 0x0]
        1. Table 47. LOW_TH_CH2 Register Field Descriptions
      34. 8.6.34  HYSTERESIS_CH3 Register (Address = 0x2C) [reset = 0xF0]
        1. Table 48. HYSTERESIS_CH3 Register Field Descriptions
      35. 8.6.35  HIGH_TH_CH3 Register (Address = 0x2D) [reset = 0xFF]
        1. Table 49. HIGH_TH_CH3 Register Field Descriptions
      36. 8.6.36  EVENT_COUNT_CH3 Register (Address = 0x2E) [reset = 0x0]
        1. Table 50. EVENT_COUNT_CH3 Register Field Descriptions
      37. 8.6.37  LOW_TH_CH3 Register (Address = 0x2F) [reset = 0x0]
        1. Table 51. LOW_TH_CH3 Register Field Descriptions
      38. 8.6.38  HYSTERESIS_CH4 Register (Address = 0x30) [reset = 0xF0]
        1. Table 52. HYSTERESIS_CH4 Register Field Descriptions
      39. 8.6.39  HIGH_TH_CH4 Register (Address = 0x31) [reset = 0xFF]
        1. Table 53. HIGH_TH_CH4 Register Field Descriptions
      40. 8.6.40  EVENT_COUNT_CH4 Register (Address = 0x32) [reset = 0x0]
        1. Table 54. EVENT_COUNT_CH4 Register Field Descriptions
      41. 8.6.41  LOW_TH_CH4 Register (Address = 0x33) [reset = 0x0]
        1. Table 55. LOW_TH_CH4 Register Field Descriptions
      42. 8.6.42  HYSTERESIS_CH5 Register (Address = 0x34) [reset = 0xF0]
        1. Table 56. HYSTERESIS_CH5 Register Field Descriptions
      43. 8.6.43  HIGH_TH_CH5 Register (Address = 0x35) [reset = 0xFF]
        1. Table 57. HIGH_TH_CH5 Register Field Descriptions
      44. 8.6.44  EVENT_COUNT_CH5 Register (Address = 0x36) [reset = 0x0]
        1. Table 58. EVENT_COUNT_CH5 Register Field Descriptions
      45. 8.6.45  LOW_TH_CH5 Register (Address = 0x37) [reset = 0x0]
        1. Table 59. LOW_TH_CH5 Register Field Descriptions
      46. 8.6.46  HYSTERESIS_CH6 Register (Address = 0x38) [reset = 0xF0]
        1. Table 60. HYSTERESIS_CH6 Register Field Descriptions
      47. 8.6.47  HIGH_TH_CH6 Register (Address = 0x39) [reset = 0xFF]
        1. Table 61. HIGH_TH_CH6 Register Field Descriptions
      48. 8.6.48  EVENT_COUNT_CH6 Register (Address = 0x3A) [reset = 0x0]
        1. Table 62. EVENT_COUNT_CH6 Register Field Descriptions
      49. 8.6.49  LOW_TH_CH6 Register (Address = 0x3B) [reset = 0x0]
        1. Table 63. LOW_TH_CH6 Register Field Descriptions
      50. 8.6.50  HYSTERESIS_CH7 Register (Address = 0x3C) [reset = 0xF0]
        1. Table 64. HYSTERESIS_CH7 Register Field Descriptions
      51. 8.6.51  HIGH_TH_CH7 Register (Address = 0x3D) [reset = 0xFF]
        1. Table 65. HIGH_TH_CH7 Register Field Descriptions
      52. 8.6.52  EVENT_COUNT_CH7 Register (Address = 0x3E) [reset = 0x0]
        1. Table 66. EVENT_COUNT_CH7 Register Field Descriptions
      53. 8.6.53  LOW_TH_CH7 Register (Address = 0x3F) [reset = 0x0]
        1. Table 67. LOW_TH_CH7 Register Field Descriptions
      54. 8.6.54  MAX_CH0_LSB Register (Address = 0x60) [reset = 0x0]
        1. Table 68. MAX_CH0_LSB Register Field Descriptions
      55. 8.6.55  MAX_CH0_MSB Register (Address = 0x61) [reset = 0x0]
        1. Table 69. MAX_CH0_MSB Register Field Descriptions
      56. 8.6.56  MAX_CH1_LSB Register (Address = 0x62) [reset = 0x0]
        1. Table 70. MAX_CH1_LSB Register Field Descriptions
      57. 8.6.57  MAX_CH1_MSB Register (Address = 0x63) [reset = 0x0]
        1. Table 71. MAX_CH1_MSB Register Field Descriptions
      58. 8.6.58  MAX_CH2_LSB Register (Address = 0x64) [reset = 0x0]
        1. Table 72. MAX_CH2_LSB Register Field Descriptions
      59. 8.6.59  MAX_CH2_MSB Register (Address = 0x65) [reset = 0x0]
        1. Table 73. MAX_CH2_MSB Register Field Descriptions
      60. 8.6.60  MAX_CH3_LSB Register (Address = 0x66) [reset = 0x0]
        1. Table 74. MAX_CH3_LSB Register Field Descriptions
      61. 8.6.61  MAX_CH3_MSB Register (Address = 0x67) [reset = 0x0]
        1. Table 75. MAX_CH3_MSB Register Field Descriptions
      62. 8.6.62  MAX_CH4_LSB Register (Address = 0x68) [reset = 0x0]
        1. Table 76. MAX_CH4_LSB Register Field Descriptions
      63. 8.6.63  MAX_CH4_MSB Register (Address = 0x69) [reset = 0x0]
        1. Table 77. MAX_CH4_MSB Register Field Descriptions
      64. 8.6.64  MAX_CH5_LSB Register (Address = 0x6A) [reset = 0x0]
        1. Table 78. MAX_CH5_LSB Register Field Descriptions
      65. 8.6.65  MAX_CH5_MSB Register (Address = 0x6B) [reset = 0x0]
        1. Table 79. MAX_CH5_MSB Register Field Descriptions
      66. 8.6.66  MAX_CH6_LSB Register (Address = 0x6C) [reset = 0x0]
        1. Table 80. MAX_CH6_LSB Register Field Descriptions
      67. 8.6.67  MAX_CH6_MSB Register (Address = 0x6D) [reset = 0x0]
        1. Table 81. MAX_CH6_MSB Register Field Descriptions
      68. 8.6.68  MAX_CH7_LSB Register (Address = 0x6E) [reset = 0x0]
        1. Table 82. MAX_CH7_LSB Register Field Descriptions
      69. 8.6.69  MAX_CH7_MSB Register (Address = 0x6F) [reset = 0x0]
        1. Table 83. MAX_CH7_MSB Register Field Descriptions
      70. 8.6.70  MIN_CH0_LSB Register (Address = 0x80) [reset = 0xFF]
        1. Table 84. MIN_CH0_LSB Register Field Descriptions
      71. 8.6.71  MIN_CH0_MSB Register (Address = 0x81) [reset = 0xFF]
        1. Table 85. MIN_CH0_MSB Register Field Descriptions
      72. 8.6.72  MIN_CH1_LSB Register (Address = 0x82) [reset = 0xFF]
        1. Table 86. MIN_CH1_LSB Register Field Descriptions
      73. 8.6.73  MIN_CH1_MSB Register (Address = 0x83) [reset = 0xFF]
        1. Table 87. MIN_CH1_MSB Register Field Descriptions
      74. 8.6.74  MIN_CH2_LSB Register (Address = 0x84) [reset = 0xFF]
        1. Table 88. MIN_CH2_LSB Register Field Descriptions
      75. 8.6.75  MIN_CH2_MSB Register (Address = 0x85) [reset = 0xFF]
        1. Table 89. MIN_CH2_MSB Register Field Descriptions
      76. 8.6.76  MIN_CH3_LSB Register (Address = 0x86) [reset = 0xFF]
        1. Table 90. MIN_CH3_LSB Register Field Descriptions
      77. 8.6.77  MIN_CH3_MSB Register (Address = 0x87) [reset = 0xFF]
        1. Table 91. MIN_CH3_MSB Register Field Descriptions
      78. 8.6.78  MIN_CH4_LSB Register (Address = 0x88) [reset = 0xFF]
        1. Table 92. MIN_CH4_LSB Register Field Descriptions
      79. 8.6.79  MIN_CH4_MSB Register (Address = 0x89) [reset = 0xFF]
        1. Table 93. MIN_CH4_MSB Register Field Descriptions
      80. 8.6.80  MIN_CH5_LSB Register (Address = 0x8A) [reset = 0xFF]
        1. Table 94. MIN_CH5_LSB Register Field Descriptions
      81. 8.6.81  MIN_CH5_MSB Register (Address = 0x8B) [reset = 0xFF]
        1. Table 95. MIN_CH5_MSB Register Field Descriptions
      82. 8.6.82  MIN_CH6_LSB Register (Address = 0x8C) [reset = 0xFF]
        1. Table 96. MIN_CH6_LSB Register Field Descriptions
      83. 8.6.83  MIN_CH6_MSB Register (Address = 0x8D) [reset = 0xFF]
        1. Table 97. MIN_CH6_MSB Register Field Descriptions
      84. 8.6.84  MIN_CH7_LSB Register (Address = 0x8E) [reset = 0xFF]
        1. Table 98. MIN_CH7_LSB Register Field Descriptions
      85. 8.6.85  MIN_CH7_MSB Register (Address = 0x8F) [reset = 0xFF]
        1. Table 99. MIN_CH7_MSB Register Field Descriptions
      86. 8.6.86  RECENT_CH0_LSB Register (Address = 0xA0) [reset = 0x0]
        1. Table 100. RECENT_CH0_LSB Register Field Descriptions
      87. 8.6.87  RECENT_CH0_MSB Register (Address = 0xA1) [reset = 0x0]
        1. Table 101. RECENT_CH0_MSB Register Field Descriptions
      88. 8.6.88  RECENT_CH1_LSB Register (Address = 0xA2) [reset = 0x0]
        1. Table 102. RECENT_CH1_LSB Register Field Descriptions
      89. 8.6.89  RECENT_CH1_MSB Register (Address = 0xA3) [reset = 0x0]
        1. Table 103. RECENT_CH1_MSB Register Field Descriptions
      90. 8.6.90  RECENT_CH2_LSB Register (Address = 0xA4) [reset = 0x0]
        1. Table 104. RECENT_CH2_LSB Register Field Descriptions
      91. 8.6.91  RECENT_CH2_MSB Register (Address = 0xA5) [reset = 0x0]
        1. Table 105. RECENT_CH2_MSB Register Field Descriptions
      92. 8.6.92  RECENT_CH3_LSB Register (Address = 0xA6) [reset = 0x0]
        1. Table 106. RECENT_CH3_LSB Register Field Descriptions
      93. 8.6.93  RECENT_CH3_MSB Register (Address = 0xA7) [reset = 0x0]
        1. Table 107. RECENT_CH3_MSB Register Field Descriptions
      94. 8.6.94  RECENT_CH4_LSB Register (Address = 0xA8) [reset = 0x0]
        1. Table 108. RECENT_CH4_LSB Register Field Descriptions
      95. 8.6.95  RECENT_CH4_MSB Register (Address = 0xA9) [reset = 0x0]
        1. Table 109. RECENT_CH4_MSB Register Field Descriptions
      96. 8.6.96  RECENT_CH5_LSB Register (Address = 0xAA) [reset = 0x0]
        1. Table 110. RECENT_CH5_LSB Register Field Descriptions
      97. 8.6.97  RECENT_CH5_MSB Register (Address = 0xAB) [reset = 0x0]
        1. Table 111. RECENT_CH5_MSB Register Field Descriptions
      98. 8.6.98  RECENT_CH6_LSB Register (Address = 0xAC) [reset = 0x0]
        1. Table 112. RECENT_CH6_LSB Register Field Descriptions
      99. 8.6.99  RECENT_CH6_MSB Register (Address = 0xAD) [reset = 0x0]
        1. Table 113. RECENT_CH6_MSB Register Field Descriptions
      100. 8.6.100 RECENT_CH7_LSB Register (Address = 0xAE) [reset = 0x0]
        1. Table 114. RECENT_CH7_LSB Register Field Descriptions
      101. 8.6.101 RECENT_CH7_MSB Register (Address = 0xAF) [reset = 0x0]
        1. Table 115. RECENT_CH7_MSB Register Field Descriptions
      102. 8.6.102 RMS_CFG Register (Address = 0xC0) [reset = 0x0]
        1. Table 116. RMS_CFG Register Field Descriptions
      103. 8.6.103 RMS_LSB Register (Address = 0xC1) [reset = 0x0]
        1. Table 117. RMS_LSB Register Field Descriptions
      104. 8.6.104 RMS_MSB Register (Address = 0xC2) [reset = 0x0]
        1. Table 118. RMS_MSB Register Field Descriptions
      105. 8.6.105 GPO0_TRIG_EVENT_SEL Register (Address = 0xC3) [reset = 0x2]
        1. Table 119. GPO0_TRIG_EVENT_SEL Register Field Descriptions
      106. 8.6.106 GPO1_TRIG_EVENT_SEL Register (Address = 0xC5) [reset = 0x2]
        1. Table 120. GPO1_TRIG_EVENT_SEL Register Field Descriptions
      107. 8.6.107 GPO2_TRIG_EVENT_SEL Register (Address = 0xC7) [reset = 0x2]
        1. Table 121. GPO2_TRIG_EVENT_SEL Register Field Descriptions
      108. 8.6.108 GPO3_TRIG_EVENT_SEL Register (Address = 0xC9) [reset = 0x2]
        1. Table 122. GPO3_TRIG_EVENT_SEL Register Field Descriptions
      109. 8.6.109 GPO4_TRIG_EVENT_SEL Register (Address = 0xCB) [reset = 0x2]
        1. Table 123. GPO4_TRIG_EVENT_SEL Register Field Descriptions
      110. 8.6.110 GPO5_TRIG_EVENT_SEL Register (Address = 0xCD) [reset = 0x2]
        1. Table 124. GPO5_TRIG_EVENT_SEL Register Field Descriptions
      111. 8.6.111 GPO6_TRIG_EVENT_SEL Register (Address = 0xCF) [reset = 0x2]
        1. Table 125. GPO6_TRIG_EVENT_SEL Register Field Descriptions
      112. 8.6.112 GPO7_TRIG_EVENT_SEL Register (Address = 0xD1) [reset = 0x2]
        1. Table 126. GPO7_TRIG_EVENT_SEL Register Field Descriptions
      113. 8.6.113 GPO_VALUE_ZCD_CFG_CH0_CH3 Register (Address = 0xE3) [reset = 0x0]
        1. Table 127. GPO_VALUE_ZCD_CFG_CH0_CH3 Register Field Descriptions
      114. 8.6.114 GPO_VALUE_ZCD_CFG_CH4_CH7 Register (Address = 0xE4) [reset = 0x0]
        1. Table 128. GPO_VALUE_ZCD_CFG_CH4_CH7 Register Field Descriptions
      115. 8.6.115 GPO_ZCD_UPDATE_EN Register (Address = 0xE7) [reset = 0x0]
        1. Table 129. GPO_ZCD_UPDATE_EN Register Field Descriptions
      116. 8.6.116 GPO_TRIGGER_CFG Register (Address = 0xE9) [reset = 0x0]
        1. Table 130. GPO_TRIGGER_CFG Register Field Descriptions
      117. 8.6.117 GPO_VALUE_TRIG Register (Address = 0xEB) [reset = 0x0]
        1. Table 131. GPO_VALUE_TRIG Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Mixed-Channel Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Digital Input
          2. 9.2.1.2.2 Digital Open-Drain Output
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Digital Push-Pull Output
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.6.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]

GENERAL_CFG is shown in Figure 39 and described in Table 16.

Return to the Summary Table.

Figure 39. GENERAL_CFG Register
7 6 5 4 3 2 1 0
RMS_EN CRC_EN STATS_EN DWC_EN CNVST CH_RST CAL RST
R/W-0b R/W-0b R/W-0b R/W-0b W-0b R/W-0b R/W-0b W-0b

Table 16. GENERAL_CFG Register Field Descriptions

Bit Field Type Reset Description
7 RMS_EN R/W 0b Enableor disable the RMS module.

0b = RMS module disabled.

1b = RMS module enabled; writing 1b to this bit clears RMS_RESULT resgiters and initiates new RMS computation.

6 CRC_EN R/W 0b Enable or disable the CRC on device interface.

0b = CRC module disabled.

1b = CRC appended to data output. CRC check is enabled on incoming data.

5 STATS_EN R/W 0b Enable or disable the statistics module to update minimum, maximum, and latest output code registers.

0b = Statistics registers are not updated.

1b = Clear statistics registers and conitnue updating with new conversion results.

4 DWC_EN R/W 0b Enable or disable the digital window comparator.

0b = Reset or disable the digital window comparator.

1b = Enable the digital window comparator.

3 CNVST W 0b Control start conversion on selected analog input. Readback of this bit returns 0b.

0b = Normal operation; conversions start on the 9th falling edge of I2C frame. Device stretches SCL until end of conversion or completion of averaging.

1b = Initiate start of conversion. Device does not stretch SCL until end of conversion or completion of averaging.

2 CH_RST R/W 0b Force all channels to be analog inputs.

0b = Normal operation.

1b = All channels are configured as analog inputs irrespective of configuration in other registers.

1 CAL R/W 0b Calibrate ADC offset.

0b = Normal operation.

1b = ADC offset is calibrated. After calibration is complete, this bit is set to 0b.

0 RST W 0b Software reset all registers to default values.

0b = Normal operation.

1b = Device is reset. After reset is complete, this bit is set to 0b and BOR bit is set to 1b.