SBAS876C
August 2018 – June 2019
ADS9224R
,
ADS9234R
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Typical Application Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: ADS92x4R
6.6
Electrical Characteristics: ADS9224R
6.7
Electrical Characteristics: ADS9234R
6.8
Timing Requirements
6.9
Switching Characteristics
6.10
Typical Characteristics: ADS9224R
6.11
Typical Characteristics: ADS9234R
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Converter Modules
7.3.1.1
Analog Input With Sample-and-Hold
7.3.1.2
ADC Transfer Function
7.3.2
Internal Reference Voltage
7.3.3
Reference Buffers
7.3.4
REFby2 Buffer
7.3.5
Data Averaging
7.3.5.1
Averaging of Two Samples
7.3.5.2
Averaging of Four Samples
7.4
Device Functional Modes
7.4.1
ACQ State
7.4.2
CNV State
7.4.3
Reset or Power-Down
7.4.3.1
Reset
7.4.3.2
Power-Down
7.4.4
Conversion Control and Data Transfer Frame
7.4.4.1
Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)
7.4.4.2
Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)
7.5
READY/STROBE Output
7.5.1
READY Output
7.5.2
STROBE Output
7.6
Programming
7.6.1
Output Data Word
7.6.2
Data Transfer Protocols
7.6.2.1
Protocols for Reading From the Device
7.6.2.1.1
Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)
7.6.2.1.2
SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)
7.6.2.1.3
SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR, SPI-x1-Q-DDR)
7.6.2.1.4
Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-DDR)
7.6.2.1.5
Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)
7.6.2.2
Device Setup
7.6.2.2.1
Single Device: All Enhanced-SPI Options
7.6.2.2.2
Single Device: Minimum Pins for a Standard SPI Interface
7.6.2.3
Protocols for Configuring the Device
7.6.3
Reading and Writing Registers
7.7
Register Maps
7.7.1
ADS92x4R Registers
7.7.1.1
DEVICE_STATUS Register (Offset = 0h) [reset = 0h]
Table 12.
DEVICE_STATUS Register Field Descriptions
7.7.1.2
POWER_DOWN_CFG Register (Offset = 1h) [reset = 0h]
Table 13.
POWER_DOWN_CFG Register Field Descriptions
7.7.1.3
PROTOCOL_CFG Register (Offset = 2h) [reset = 0h]
Table 14.
PROTOCOL_CFG Register Field Descriptions
7.7.1.4
BUS_WIDTH Register (Offset = 3h) [reset = 0h]
Table 15.
BUS_WIDTH Register Field Descriptions
7.7.1.5
CRT_CFG Register (Offset = 4h) [reset = 0h]
Table 16.
CRT_CFG Register Field Descriptions
7.7.1.6
OUTPUT_DATA_WORD_CFG Register (Offset = 5h) [reset = 0h]
Table 17.
OUTPUT_DATA_WORD_CFG Register Field Descriptions
7.7.1.7
DATA_AVG_CFG Register (Offset = 6h) [reset = 0h]
Table 18.
DATA_AVG_CFG Register Field Descriptions
7.7.1.8
REFBY2_OFFSET Register (Offset = 7h) [reset = 0h]
Table 19.
REFBY2_OFFSET Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.1.1
ADC Input Driver
8.1.1.1
Charge-Kickback Filter
8.1.2
Input Amplifier Selection
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Signal Path
10.1.2
Grounding and PCB Stack-Up
10.1.3
Decoupling of Power Supplies
10.1.4
Reference Decoupling
10.1.5
Differential Input Decoupling
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.2
Related Documentation
11.3
Related Links
11.4
Receiving Notification of Documentation Updates
11.5
Community Resources
11.6
Trademarks
11.7
Electrostatic Discharge Caution
11.8
Glossary
12
Mechanical, Packaging, and Orderable Information
11
Device and Documentation Support