SBAS883A February 2018 – June 2018 OPT3101
PRODUCTION DATA.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EN_FREQ_CORR | EN_FLOOP | EN_AUTO_FREQ_COUNT | SYS_CLK_DIVIDER | START_FREQ_CALIB | |||
R/W - 0h | R/W - 0h | R/W - 0h | R/W - Ah | R/W - 0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | REF_COUNT_LIMIT | ||||||
R/W - 0h | R/W - 4Ch | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF_COUNT_LIMIT | |||||||
R/W - 4Bh |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23 | EN_FREQ_CORR | R/W | 0h | Enable frequency correction for the phase output.
0: Frequency correction disabled | 1: Frequency correction enabled |
22 | EN_FLOOP | R/W | 0h | Enables the frequency calibration block.
0: Disable frequency calibration block | 1: Enable frequency calibration block |
21 | EN_AUTO_FREQ_COUNT | R/W | 0h | Determines the value to be used for frequency correction.
0 – On-chip trimmed value | 1 – Measured value from frequency calibration |
20:17 | SYS_CLK_DIVIDER | R/W | Ah | Programs the system-clock divider for frequency calibration. This register should be adjusted to get it closer to the external reference frequency connected to GP2 pin.
SYS_CLK_DIVIDER = round(log2(40 × 106 / fEXT)) |
16 | START_FREQ_CALIB | R/W | 0h | Setting this bit to 1 starts the frequency calibration. |
15 | RESERVED | R/W | 0h | Always read or write 0h. |
14:0 | REF_COUNT_LIMIT | R/W | 4C4Bh | This sets the limit for ref-clock count.
REF_COUNT_LIMIT = (40 × 106 / 2SYS_CLK_DIVIDER) / fEXT |