SBAS888B December 2020 – July 2022 ADC3664
PRODUCTION DATA
In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential signaling with a high slew rate. This is especially important in IF sampling applications (Figure 8-8 and Figure 8-9). For less jitter sensitive applications, the ADC3664 provides the option to operate with single ended signaling which saves additional power consumption.