SBAS891B November   2017  – September 2022 ADS7142-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Modes
    6. 6.6  Electrical Characteristics: Manual Mode
    7. 6.7  Electrical Characteristics: Autonomous Modes
    8. 6.8  Electrical Characteristics: High Precision Mode
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics: All Modes
    13. 6.13 Typical Characteristics: Manual Mode
    14. 6.14 Typical Characteristics: Autonomous Modes
    15. 6.15 Typical Characteristics: High-Precision Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
        1. 7.3.1.1 Two-Channel, Single-Ended Configuration
        2. 7.3.1.2 Single-Channel, Single-Ended Configuration With Remote Ground Sense
        3. 7.3.1.3 Single-Channel, Pseudo-Differential Configuration
      2. 7.3.2  Offset Calibration
      3. 7.3.3  Reference
      4. 7.3.4  ADC Transfer Function
      5. 7.3.5  Oscillator and Timing Control
      6. 7.3.6  I2C Address Selector
      7. 7.3.7  Data Buffer
        1. 7.3.7.1 Filling of the Data Buffer
        2. 7.3.7.2 Reading Data From the Data Buffer
      8. 7.3.8  Accumulator
      9. 7.3.9  Digital Window Comparator
      10. 7.3.10 I2C Protocol Features
        1. 7.3.10.1 General Call
        2. 7.3.10.2 General Call With Software Reset
        3. 7.3.10.3 General Call With Write Software Programmable Part of the Target Address
        4. 7.3.10.4 Configuring the ADC Into High-Speed I2C Mode
        5. 7.3.10.5 Bus Clear
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power Up and Reset
      2. 7.4.2 Manual Mode
        1. 7.4.2.1 Manual Mode With CH0 Only
        2. 7.4.2.2 Manual Mode With AUTO Sequence
      3. 7.4.3 Autonomous Modes
        1. 7.4.3.1 Autonomous Mode With Threshold Monitoring and Diagnostics
          1. 7.4.3.1.1 Autonomous Mode With Pre-ALERT Data
          2. 7.4.3.1.2 Autonomous Mode With Post-ALERT Data
        2. 7.4.3.2 Autonomous Mode With Burst Data
          1. 7.4.3.2.1 Autonomous Mode With Start Burst
          2. 7.4.3.2.2 Autonomous Mode With Stop Burst
      4. 7.4.4 High-Precision Mode
    5. 7.5 Programming
      1. 7.5.1 Reading Registers
        1. 7.5.1.1 Single Register Read
        2. 7.5.1.2 Reading a Continuous Block of Registers
      2. 7.5.2 Writing Registers
        1. 7.5.2.1 Single Register Write
        2. 7.5.2.2 Writing a Continuous Block of Registers
        3. 7.5.2.3 Set Bit
        4. 7.5.2.4 Clear Bit
    6. 7.6 Register Map
      1. 7.6.1 Page1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 ADS7142-Q1 as a Programmable Comparator With False Trigger Prevention and Diagnostics
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Programmable Thresholds and Hysteresis
          2. 8.2.1.2.2 False Trigger Prevention With an Event Counter
          3. 8.2.1.2.3 Fault Diagnostics With the Data Buffer
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Voltage and Temperature Monitoring in Remote Camera Modules Using the ADS7142-Q1
        1. 8.2.2.1 Design Requirements
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD and DVDD Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Electrostatic Discharge Caution
    2. 9.2 Glossary
    3. 9.3 Trademarks
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
  10. 10Mechanical, Packaging, and Orderable Information

7.3.9 Digital Window Comparator

The internal digital window comparator is available in all modes. In autonomous modes with thresholds monitoring and diagnostics, the digital window comparator controls the filling of the data into the FIFO and the output of the ALERT pin. In the remaining modes, the digital window comparator only controls the output of the ALERT pin. Figure 7-9 provides the block diagram for digital window comparator.

GUID-015C2E39-3F07-44CE-942C-C65C55FB7F02-low.gifFigure 7-9 Digital Comparator Block Diagram

The low-side threshold, high-side threshold, and hysteresis parameters are independently programmable for each input channel. Figure 7-10 illustrates the comparison thresholds and hysteresis for the two comparators. A pre-ALERT event counter after each comparator counts the output of the comparator and sets the latched flags. The pre-ALERT event counter settings are common to the two channels.

GUID-ED07BF4E-6DB0-4B3F-AF7D-9FD829E6D6B1-low.gifFigure 7-10 Thresholds, Hysteresis, and Event Counter for the Digital Window Comparator

The DWC_BLOCK_EN bit in the ALERT_DWC_EN register enables and disables the complete digital window comparator block (disabled at power-up) and the ALERT_EN_CHx bits in the ALERT_CHEN register enables the digital window comparator for individual channels. Possible responses when using the digital comparator when a new ADC conversion is completed include:

  1. The output of the high-side comparator transitions to a logic high when the conversion result is greater than the high threshold. This comparator resets when the conversion result is less than the high threshold – hysteresis.
  2. The output of the low-side comparator transitions to a logic high when the conversion result is less than the low threshold. This comparator resets when the conversion result is greater than the low threshold + hysteresis.
  3. When the output of either the high-side or low-side comparator transitions high, the pre-ALERT event counter begins to increment for each subsequent conversion. This counter continues to increment until the value stored in the PRE_ALT_MAX_EVENT_COUNT register is reached. When the counter reaches PRE_ALT_MAX_EVENT_COUNT, the alert becomes active and sets the latched flags. If the comparator output becomes zero before the counter reaches PRE_ALT_MAX_EVENT_COUNT, then the event counter is reset to zero, ALERT is not set, and the latched flag is not set.

Therefore, the latched flags (high and low) for the channel are updated only if the respective comparator output remains 1 for the specified number of consecutive conversions (set by PRE_ALT_MAX_EVENT_COUNT).

The latched flags can be read from the ALERT_LOW_FLAGS and ALERT_HIGH_FLAGS registers. To clear a latched flag, write 1 to the applicable bit location. The ALERT pin status is re-evaluated when an applicable latched flag is set or is cleared.

The response time for the ALERT pin can be estimated by Equation 6

Equation 6. tresponse = [1 + k × (PRE_ALT_MAX_EVENT_COUNT + 1) ] × nCLK × Oscillator TimePeriod

where:

  • k = Number of channels enabled in device sequence
  • nCLK = Number of clocks used by device for one conversion cycle
  • Oscillator timer period = tLPO or tHSO depending on the OSC_SEL value; see the Section 6 section for tLPO or tHSO