SBAS940
December 2018
DAC8742H
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
HART Modulator
7.3.2
HART Demodulator
7.3.3
FOUNDATION FIELDBUS / PROFIBUS PA Manchester Encoder
7.3.4
FOUNDATION FIELDBUS / PROFIBUS PA Manchester Decoder
7.3.5
Internal Reference
7.3.6
Clock Configuration
7.3.7
Reset and Power-Down
7.3.8
Full-Duplex Mode
7.3.9
I/O Selection
7.3.10
Jabber Inhibitor
7.4
Device Functional Modes
7.4.1
UART Interfaced HART
7.4.2
UART Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
7.4.3
SPI Interfaced HART
7.4.4
SPI Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
7.4.5
Interface
7.4.5.1
UART
7.4.5.1.1
UART Carrier Detect
7.4.5.2
SPI
7.4.5.2.1
SPI Cyclic Redundancy Check
7.4.5.2.2
SPI Interrupt Request
7.5
Register Maps
7.5.1
CONTROL Register (Offset = 2h) [reset = 0x8042]
Table 4.
CONTROL Register Field Descriptions
7.5.2
RESET Register (Offset = 7h) [reset = 0x0000]
Table 5.
RESET Register Field Descriptions
7.5.3
MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
Table 6.
MODEM_STATUS Register Field Descriptions
7.5.4
MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
Table 7.
MODEM_IRQ_MASK Register Field Descriptions
7.5.5
MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
Table 8.
MODEM_CONTROL Register Field Descriptions
7.5.6
FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
Table 9.
FIFO_D2M Register Field Descriptions
7.5.7
FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
Table 10.
FIFO_M2D Register Field Descriptions
7.5.8
FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
Table 11.
FIFO_LEVEL_SET Register Field Descriptions
7.5.9
PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
Table 12.
PAFF_JABBER Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.1.1
Design Recommendations
8.1.2
Selecting the Crystal/Resonator
8.1.3
Included Functions and Filter Selection
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
DAC8742H HART Modem
8.2.2.2
2-Wire Current Loop
8.2.2.3
Regulator
8.2.2.4
DAC
8.2.2.5
Amplifiers
8.2.2.6
Diodes
8.2.2.7
Passives
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
1
Features
HART-Compliant Physical Layer Modem
1200/2200 Hz HART FSK Sinusoids
Register Programmable Amplitude of TX Signals
(DAC8741H / DAC8742H only)
Integrated RX Demodulator and Band-Pass Filter with Minimal External Components
FOUNDATION Fieldbus Compatible H1 Controller and Medium Attachment Unit (MAU)
31.25 kbit/s Communication Based on Manchester Coded Bus Powered (MBP)
Integrated Manchester Encoder and Decoder
Compatible with PROFIBUS PA
Low Quiescent Current: 180 uA Max at Typical Industrial Operating Temperature Range (-40°C to 85°C)
Integrated 1.5-V Reference
Flexible Clocking Options
Internal Oscillator
External Crystal Oscillator
External CMOS Clock
Digital Interface
DAC8742H: UART and SPI
Reliability: CRC Bit Error Checking, Watchdog Timer
Wide Operating Temperature: –55°C to 125°C
5 mm x 5 mm TQFP Package