SBAS993B May   2019  – October 2019 TLV320ADC3140

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: SPI Interface
    9. 7.9  Switching Characteristics: SPI Interface
    10. 7.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 7.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 7.12 Timing Requirements: PDM Digital Microphone Interface
    13. 7.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 7.14 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3 Input Channel Configurations
      4. 8.3.4 Reference Voltage
      5. 8.3.5 Programmable Microphone Bias
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.6.2 Programmable Channel Gain Calibration
        3. 8.3.6.3 Programmable Channel Phase Calibration
        4. 8.3.6.4 Programmable Digital High-Pass Filter
        5. 8.3.6.5 Programmable Digital Biquad Filters
        6. 8.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.6.7 Configurable Digital Decimation Filters
          1. 8.3.6.7.1 Linear Phase Filters
            1. 8.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
          2. 8.3.6.7.2 Low-Latency Filters
            1. 8.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
          3. 8.3.6.7.3 Ultra-Low-Latency Filters
            1. 8.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
            7. 8.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
      7. 8.3.7 Automatic Gain Controller (AGC)
      8. 8.3.8 Digital PDM Microphone Record Channel
      9. 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Shutdown
      2. 8.4.2 Sleep Mode or Software Shutdown
      3. 8.4.3 Active Mode
      4. 8.4.4 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
        2. 8.5.1.2 SPI Control Interface
          1. Table 1. SPI Command Word
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 Register Descriptions
          1. 8.6.1.1.1  PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
            1. Table 51. PAGE_CFG Register Field Descriptions
          2. 8.6.1.1.2  SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
            1. Table 52. SW_RESET Register Field Descriptions
          3. 8.6.1.1.3  SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
            1. Table 53. SLEEP_CFG Register Field Descriptions
          4. 8.6.1.1.4  SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
            1. Table 54. SHDN_CFG Register Field Descriptions
          5. 8.6.1.1.5  ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
            1. Table 55. ASI_CFG0 Register Field Descriptions
          6. 8.6.1.1.6  ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
            1. Table 56. ASI_CFG1 Register Field Descriptions
          7. 8.6.1.1.7  ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
            1. Table 57. ASI_CFG2 Register Field Descriptions
          8. 8.6.1.1.8  ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
            1. Table 58. ASI_CH1 Register Field Descriptions
          9. 8.6.1.1.9  ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
            1. Table 59. ASI_CH2 Register Field Descriptions
          10. 8.6.1.1.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
            1. Table 60. ASI_CH3 Register Field Descriptions
          11. 8.6.1.1.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
            1. Table 61. ASI_CH4 Register Field Descriptions
          12. 8.6.1.1.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
            1. Table 62. ASI_CH5 Register Field Descriptions
          13. 8.6.1.1.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
            1. Table 63. ASI_CH6 Register Field Descriptions
          14. 8.6.1.1.14 ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
            1. Table 64. ASI_CH7 Register Field Descriptions
          15. 8.6.1.1.15 ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
            1. Table 65. ASI_CH8 Register Field Descriptions
          16. 8.6.1.1.16 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
            1. Table 66. MST_CFG0 Register Field Descriptions
          17. 8.6.1.1.17 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
            1. Table 67. MST_CFG1 Register Field Descriptions
          18. 8.6.1.1.18 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
            1. Table 68. ASI_STS Register Field Descriptions
          19. 8.6.1.1.19 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
            1. Table 69. CLK_SRC Register Field Descriptions
          20. 8.6.1.1.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
            1. Table 70. PDMCLK_CFG Register Field Descriptions
          21. 8.6.1.1.21 PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
            1. Table 71. PDMIN_CFG Register Field Descriptions
          22. 8.6.1.1.22 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
            1. Table 72. GPIO_CFG0 Register Field Descriptions
          23. 8.6.1.1.23 GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
            1. Table 73. GPO_CFG0 Register Field Descriptions
          24. 8.6.1.1.24 GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
            1. Table 74. GPO_CFG1 Register Field Descriptions
          25. 8.6.1.1.25 GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
            1. Table 75. GPO_CFG2 Register Field Descriptions
          26. 8.6.1.1.26 GPO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
            1. Table 76. GPO_CFG3 Register Field Descriptions
          27. 8.6.1.1.27 GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
            1. Table 77. GPO_VAL Register Field Descriptions
          28. 8.6.1.1.28 GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
            1. Table 78. GPIO_MON Register Field Descriptions
          29. 8.6.1.1.29 GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
            1. Table 79. GPI_CFG0 Register Field Descriptions
          30. 8.6.1.1.30 GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
            1. Table 80. GPI_CFG1 Register Field Descriptions
          31. 8.6.1.1.31 GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
            1. Table 81. GPI_MON Register Field Descriptions
          32. 8.6.1.1.32 INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
            1. Table 82. INT_CFG Register Field Descriptions
          33. 8.6.1.1.33 INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
            1. Table 83. INT_MASK0 Register Field Descriptions
          34. 8.6.1.1.34 INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
            1. Table 84. INT_LTCH0 Register Field Descriptions
          35. 8.6.1.1.35 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
            1. Table 85. BIAS_CFG Register Field Descriptions
          36. 8.6.1.1.36 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
            1. Table 86. CH1_CFG0 Register Field Descriptions
          37. 8.6.1.1.37 CH1_CFG1 Register (page = 0x00, address = 0x3D) [reset = 0h]
            1. Table 87. CH1_CFG1 Register Field Descriptions
          38. 8.6.1.1.38 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
            1. Table 88. CH1_CFG2 Register Field Descriptions
          39. 8.6.1.1.39 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
            1. Table 89. CH1_CFG3 Register Field Descriptions
          40. 8.6.1.1.40 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
            1. Table 90. CH1_CFG4 Register Field Descriptions
          41. 8.6.1.1.41 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
            1. Table 91. CH2_CFG0 Register Field Descriptions
          42. 8.6.1.1.42 CH2_CFG1 Register (page = 0x00, address = 0x42) [reset = 0h]
            1. Table 92. CH2_CFG1 Register Field Descriptions
          43. 8.6.1.1.43 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
            1. Table 93. CH2_CFG2 Register Field Descriptions
          44. 8.6.1.1.44 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
            1. Table 94. CH2_CFG3 Register Field Descriptions
          45. 8.6.1.1.45 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
            1. Table 95. CH2_CFG4 Register Field Descriptions
          46. 8.6.1.1.46 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
            1. Table 96. CH3_CFG0 Register Field Descriptions
          47. 8.6.1.1.47 CH3_CFG1 Register (page = 0x00, address = 0x47) [reset = 0h]
            1. Table 97. CH3_CFG1 Register Field Descriptions
          48. 8.6.1.1.48 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
            1. Table 98. CH3_CFG2 Register Field Descriptions
          49. 8.6.1.1.49 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
            1. Table 99. CH3_CFG3 Register Field Descriptions
          50. 8.6.1.1.50 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
            1. Table 100. CH3_CFG4 Register Field Descriptions
          51. 8.6.1.1.51 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
            1. Table 101. CH4_CFG0 Register Field Descriptions
          52. 8.6.1.1.52 CH4_CFG1 Register (page = 0x00, address = 0x4C) [reset = 0h]
            1. Table 102. CH4_CFG1 Register Field Descriptions
          53. 8.6.1.1.53 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
            1. Table 103. CH4_CFG2 Register Field Descriptions
          54. 8.6.1.1.54 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
            1. Table 104. CH4_CFG3 Register Field Descriptions
          55. 8.6.1.1.55 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
            1. Table 105. CH4_CFG4 Register Field Descriptions
          56. 8.6.1.1.56 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
            1. Table 106. CH5_CFG2 Register Field Descriptions
          57. 8.6.1.1.57 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
            1. Table 107. CH5_CFG3 Register Field Descriptions
          58. 8.6.1.1.58 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
            1. Table 108. CH5_CFG4 Register Field Descriptions
          59. 8.6.1.1.59 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
            1. Table 109. CH6_CFG2 Register Field Descriptions
          60. 8.6.1.1.60 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
            1. Table 110. CH6_CFG3 Register Field Descriptions
          61. 8.6.1.1.61 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
            1. Table 111. CH6_CFG4 Register Field Descriptions
          62. 8.6.1.1.62 CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
            1. Table 112. CH7_CFG2 Register Field Descriptions
          63. 8.6.1.1.63 CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
            1. Table 113. CH7_CFG3 Register Field Descriptions
          64. 8.6.1.1.64 CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
            1. Table 114. CH7_CFG4 Register Field Descriptions
          65. 8.6.1.1.65 CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
            1. Table 115. CH8_CFG2 Register Field Descriptions
          66. 8.6.1.1.66 CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
            1. Table 116. CH8_CFG3 Register Field Descriptions
          67. 8.6.1.1.67 CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
            1. Table 117. CH8_CFG4 Register Field Descriptions
          68. 8.6.1.1.68 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
            1. Table 118. DSP_CFG0 Register Field Descriptions
          69. 8.6.1.1.69 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
            1. Table 119. DSP_CFG1 Register Field Descriptions
          70. 8.6.1.1.70 AGC_CFG0 Register (page = 0x00, address = 0x70) [reset = E7h]
            1. Table 120. AGC_CFG0 Register Field Descriptions
          71. 8.6.1.1.71 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
            1. Table 121. IN_CH_EN Register Field Descriptions
          72. 8.6.1.1.72 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
            1. Table 122. ASI_OUT_CH_EN Register Field Descriptions
          73. 8.6.1.1.73 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
            1. Table 123. PWR_CFG Register Field Descriptions
          74. 8.6.1.1.74 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
            1. Table 124. DEV_STS0 Register Field Descriptions
          75. 8.6.1.1.75 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
            1. Table 125. DEV_STS1 Register Field Descriptions
          76. 8.6.1.1.76 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
            1. Table 126. I2C_CKSUM Register Field Descriptions
      2. 8.6.2 Programmable Coefficient Registers
        1. 8.6.2.1 Programmable Coefficient Registers: Page = 0x02
        2. 8.6.2.2 Programmable Coefficient Registers: Page = 0x03
        3. 8.6.2.3 Programmable Coefficient Registers: Page = 0x04
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Four-Channel Analog Microphone Recording
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Eight-Channel Digital PDM Microphone Recording
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.6.2.3 Programmable Coefficient Registers: Page = 0x04

This register page (shown in Table 129) consists of the programmable coefficients for mixer 1 to mixer 4 and the first-order IIR filter.

Table 129. Page 0x04 Programmable Coefficient Registers

ADDR REGISTER RESET DESCRIPTION
0x00 PAGE[7:0] 0x00 Device page register
0x08 MIX1_CH1_BYT1[7:0] 0x7F Digital mixer 1, channel 1 coefficient byte[31:24]
0x09 MIX1_CH1_BYT2[7:0] 0xFF Digital mixer 1, channel 1 coefficient byte[23:16]
0x0A MIX1_CH1_BYT3[7:0] 0xFF Digital mixer 1, channel 1 coefficient byte[15:8]
0x0B MIX1_CH1_BYT4[7:0] 0xFF Digital mixer 1, channel 1 coefficient byte[7:0]
0x0C MIX1_CH2_BYT1[7:0] 0x00 Digital mixer 1, channel 2 coefficient byte[31:24]
0x0D MIX1_CH2_BYT2[7:0] 0x00 Digital mixer 1, channel 2 coefficient byte[23:16]
0x0E MIX1_CH2_BYT3[7:0] 0x00 Digital mixer 1, channel 2 coefficient byte[15:8]
0x0F MIX1_CH2_BYT4[7:0] 0x00 Digital mixer 1, channel 2 coefficient byte[7:0]
0x10 MIX1_CH3_BYT1[7:0] 0x00 Digital mixer 1, channel 3 coefficient byte[31:24]
0x11 MIX1_CH3_BYT2[7:0] 0x00 Digital mixer 1, channel 3 coefficient byte[23:16]
0x12 MIX1_CH3_BYT3[7:0] 0x00 Digital mixer 1, channel 3 coefficient byte[15:8]
0x13 MIX1_CH3_BYT4[7:0] 0x00 Digital mixer 1, channel 3 coefficient byte[7:0]
0x14 MIX1_CH4_BYT1[7:0] 0x00 Digital mixer 1, channel 4 coefficient byte[31:24]
0x15 MIX1_CH4_BYT2[7:0] 0x00 Digital mixer 1, channel 4 coefficient byte[23:16]
0x16 MIX1_CH4_BYT3[7:0] 0x00 Digital mixer 1, channel 4 coefficient byte[15:8]
0x17 MIX1_CH4_BYT4[7:0] 0x00 Digital mixer 1, channel 4 coefficient byte[7:0]
0x18 MIX2_CH1_BYT1[7:0] 0x00 Digital mixer 2, channel 1 coefficient byte[31:24]
0x19 MIX2_CH1_BYT2[7:0] 0x00 Digital mixer 2, channel 1 coefficient byte[23:16]
0x1A MIX2_CH1_BYT3[7:0] 0x00 Digital mixer 2, channel 1 coefficient byte[15:8]
0x1B MIX2_CH1_BYT4[7:0] 0x00 Digital mixer 2, channel 1 coefficient byte[7:0]
0x1C MIX2_CH2_BYT1[7:0] 0x7F Digital mixer 2, channel 2 coefficient byte[31:24]
0x1D MIX2_CH2_BYT2[7:0] 0xFF Digital mixer 2, channel 2 coefficient byte[23:16]
0x1E MIX2_CH2_BYT3[7:0] 0xFF Digital mixer 2, channel 2 coefficient byte[15:8]
0x1F MIX2_CH2_BYT4[7:0] 0xFF Digital mixer 2, channel 2 coefficient byte[7:0]
0x20 MIX2_CH3_BYT1[7:0] 0x00 Digital mixer 2, channel 3 coefficient byte[31:24]
0x21 MIX2_CH3_BYT2[7:0] 0x00 Digital mixer 2, channel 3 coefficient byte[23:16]
0x22 MIX2_CH3_BYT3[7:0] 0x00 Digital mixer 2, channel 3 coefficient byte[15:8]
0x23 MIX2_CH3_BYT4[7:0] 0x00 Digital mixer 2, channel 3 coefficient byte[7:0]
0x24 MIX2_CH4_BYT1[7:0] 0x00 Digital mixer 2, channel 4 coefficient byte[31:24]
0x25 MIX2_CH4_BYT2[7:0] 0x00 Digital mixer 2, channel 4 coefficient byte[23:16]
0x26 MIX2_CH4_BYT3[7:0] 0x00 Digital mixer 2, channel 4 coefficient byte[15:8]
0x27 MIX2_CH4_BYT4[7:0] 0x00 Digital mixer 2, channel 4 coefficient byte[7:0]
0x28 MIX3_CH1_BYT1[7:0] 0x00 Digital mixer 3, channel 1 coefficient byte[31:24]
0x29 MIX3_CH1_BYT2[7:0] 0x00 Digital mixer 3, channel 1 coefficient byte[23:16]
0x2A MIX3_CH1_BYT3[7:0] 0x00 Digital mixer 3, channel 1 coefficient byte[15:8]
0x2B MIX3_CH1_BYT4[7:0] 0x00 Digital mixer 3, channel 1 coefficient byte[7:0]
0x2C MIX3_CH2_BYT1[7:0] 0x00 Digital mixer 3, channel 2 coefficient byte[31:24]
0x2D MIX3_CH2_BYT2[7:0] 0x00 Digital mixer 3, channel 2 coefficient byte[23:16]
0x2E MIX3_CH2_BYT3[7:0] 0x00 Digital mixer 3, channel 2 coefficient byte[15:8]
0x2F MIX3_CH2_BYT4[7:0] 0x00 Digital mixer 3, channel 2 coefficient byte[7:0]
0x30 MIX3_CH3_BYT1[7:0] 0x7F Digital mixer 3, channel 3 coefficient byte[31:24]
0x31 MIX3_CH3_BYT2[7:0] 0xFF Digital mixer 3, channel 3 coefficient byte[23:16]
0x32 MIX3_CH3_BYT3[7:0] 0xFF Digital mixer 3, channel 3 coefficient byte[15:8]
0x33 MIX3_CH3_BYT4[7:0] 0xFF Digital mixer 3, channel 3 coefficient byte[7:0]
0x34 MIX3_CH4_BYT1[7:0] 0x00 Digital mixer 3, channel 4 coefficient byte[31:24]
0x35 MIX3_CH4_BYT2[7:0] 0x00 Digital mixer 3, channel 4 coefficient byte[23:16]
0x36 MIX3_CH4_BYT3[7:0] 0x00 Digital mixer 3, channel 4 coefficient byte[15:8]
0x37 MIX3_CH4_BYT4[7:0] 0x00 Digital mixer 3, channel 4 coefficient byte[7:0]
0x38 MIX4_CH1_BYT1[7:0] 0x00 Digital mixer 4, channel 1 coefficient byte[31:24]
0x39 MIX4_CH1_BYT2[7:0] 0x00 Digital mixer 4, channel 1 coefficient byte[23:16]
0x3A MIX4_CH1_BYT3[7:0] 0x00 Digital mixer 4, channel 1 coefficient byte[15:8]
0x3B MIX4_CH1_BYT4[7:0] 0x00 Digital mixer 4, channel 1 coefficient byte[7:0]
0x3C MIX4_CH2_BYT1[7:0] 0x00 Digital mixer 4, channel 2 coefficient byte[31:24]
0x3D MIX4_CH2_BYT2[7:0] 0x00 Digital mixer 4, channel 2 coefficient byte[23:16]
0x3E MIX4_CH2_BYT3[7:0] 0x00 Digital mixer 4, channel 2 coefficient byte[15:8]
0x3F MIX4_CH2_BYT4[7:0] 0x00 Digital mixer 4, channel 2 coefficient byte[7:0]
0x40 MIX4_CH3_BYT1[7:0] 0x00 Digital mixer 4, channel 3 coefficient byte[31:24]
0x41 MIX4_CH3_BYT2[7:0] 0x00 Digital mixer 4, channel 3 coefficient byte[23:16]
0x42 MIX4_CH3_BYT3[7:0] 0x00 Digital mixer 4, channel 3 coefficient byte[15:8]
0x43 MIX4_CH3_BYT4[7:0] 0x00 Digital mixer 4, channel 3 coefficient byte[7:0]
0x44 MIX4_CH4_BYT1[7:0] 0x7F Digital mixer 4, channel 4 coefficient byte[31:24]
0x45 MIX4_CH4_BYT2[7:0] 0xFF Digital mixer 4, channel 4 coefficient byte[23:16]
0x46 MIX4_CH4_BYT3[7:0] 0xFF Digital mixer 4, channel 4 coefficient byte[15:8]
0x47 MIX4_CH4_BYT4[7:0] 0xFF Digital mixer 4, channel 4 coefficient byte[7:0]
0x48 IIR_N0_BYT1[7:0] 0x7F Programmable first-order IIR, N0 coefficient byte[31:24]
0x49 IIR_N0_BYT2[7:0] 0xFF Programmable first-order IIR, N0 coefficient byte[23:16]
0x4A IIR_N0_BYT3[7:0] 0xFF Programmable first-order IIR, N0 coefficient byte[15:8]
0x4B IIR_N0_BYT4[7:0] 0xFF Programmable first-order IIR, N0 coefficient byte[7:0]
0x4C IIR_N1_BYT1[7:0] 0x00 Programmable first-order IIR, N1 coefficient byte[31:24]
0x4D IIR_N1_BYT2[7:0] 0x00 Programmable first-order IIR, N1 coefficient byte[23:16]
0x4E IIR_N1_BYT3[7:0] 0x00 Programmable first-order IIR, N1 coefficient byte[15:8]
0x4F IIR_N1_BYT4[7:0] 0x00 Programmable first-order IIR, N1 coefficient byte[7:0]
0x50 IIR_D1_BYT1[7:0] 0x00 Programmable first-order IIR, D1 coefficient byte[31:24]
0x51 IIR_D1_BYT2[7:0] 0x00 Programmable first-order IIR, D1 coefficient byte[23:16]
0x52 IIR_D1_BYT3[7:0] 0x00 Programmable first-order IIR, D1 coefficient byte[15:8]
0x53 IIR_D1_BYT4[7:0] 0x00 Programmable first-order IIR, D1 coefficient byte[7:0]