SBASA01B September   2020  – March 2022 ADC3660

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 SDR Output Clocking
        2. 8.3.5.2 Output Data Format
        3. 8.3.5.3 Output Formatter
        4. 8.3.5.4 Output Bit Mapper
        5. 8.3.5.5 Output Interface/Mode Configuration
          1. 8.3.5.5.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.7 Electrical Characteristics - AC Specifications

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NSD Noise Spectral Density fIN = 1.1 MHz, AIN = -20 dBFS -159 dBFS/Hz
SNR(1) Signal to noise ratio fIN = 1.1 MHz 82.0 dBFS
fIN = 5 MHz 77.5 81.9
fIN = 10 MHz 81.2
fIN = 20 MHz 79.9
fIN = 40 MHz 77.6
fIN = 64 MHz 74.6
SNR Signal to noise ratio, complex decimation by 16 fIN = 1.1 MHz, fNCO = 2.5 MHz 88.3 dBFS
fIN = 5 MHz, fNCO = 5 MHz 89.2
fIN = 10 MHz, fNCO = 10 MHz 89.3
fIN = 20 MHz, fNCO = 20 MHz 88.7
fIN = 40 MHz, fNCO = 40 MHz 86.5
fIN = 64 MHz, fNCO = 62.6 MHz 84.3
SINAD(1) Signal to noise and distortion ratio fIN = 1.1 MHz 80.0 dBFS
fIN = 5 MHz 76.2 80.9
fIN = 10 MHz 80.8
fIN = 20 MHz 78.1
fIN = 40 MHz 76.2
fIN = 64 MHz 73.6
ENOB(1) Effective number of bits fIN = 1.1 MHz 13.3 bit
fIN = 5 MHz 12.6 13.3
fIN = 10 MHz 13.2
fIN = 20 MHz 13.0
fIN = 40 MHz 12.6
fIN = 64 MHz 12.1
THD(1) Total Harmonic Distortion (First five harmonics) fIN = 1.1 MHz 83 dBc
fIN = 5 MHz 81 87
fIN = 10 MHz 90
fIN = 20 MHz 82
fIN = 40 MHz 81
fIN = 64 MHz 80
SFDR(1) Spur free dynamic range including second and third harmonic fIN = 1.1 MHz 84 dBc
fIN = 5 MHz 83 88
fIN = 10 MHz 94
fIN = 20 MHz 85
fIN = 40 MHz 83
fIN = 64 MHz 84 dBc
Non HD2,3(1) Spur free dynamic range (excluding HD2 and HD3) fIN = 1.1 MHz 101 dBFS
fIN = 5 MHz 91 102
fIN = 10 MHz 99
fIN = 20 MHz 95
fIN = 40 MHz 93
fIN = 64 MHz 87
IMD3 Two tone inter-modulation distortion f1 = 3 MHz, f2 = 4 MHz, AIN = -7 dBFS/tone 88 dBc
f1 = 10 MHz, f2 = 12 MHz, AIN = -7 dBFS/tone 90
(1) Performance data shown is prior to decimation filtering. With DDC enabled, performance improves by the decimation filtering process.