5 Description (continued)

The AFE58JD48 is an integrated AFE optimized for premium medical ultrasound application. The device is realized through a multichip module (MCM) with three dies: one 16-CH voltage-controlled amplifier (VCA) die and two 8-CH analog-to-digital converter (ADC) dies.

Each channel in the VCA die can be configured in one of two modes: time gain compensation (TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes a low-noise amplifier (LNA), a voltage-controlled attenuator (VCAT), a programmable gain amplifier (PGA), and a third-order, low-pass filter (LPF). The LNA is programmable in gains of 21 dB, 18 dB, or 15 dB. The LNA also supports active termination. The VCAT supports an attenuation range of 0 dB to 36 dB, with analog voltage control for the attenuation. The PGA provides gain options from 18 dB to 27 dB in steps of 3 dB. The LPF cutoff frequency can be set between 10 MHz and 60 MHz to support ultrasound applications with different frequencies, especially the emerging high frequency ultrasound imaging applications. In CW mode, the output of the LNA goes to a low-power passive mixer with 16 selectable phase delays followed by a summing amplifier with a band-pass filter. Different phase delays can be applied to each analog input signal to perform an on-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance the sensitivity of the CW Doppler measurement.

The ADC die can be configured to operate with a resolution of 16 bits or 14 bits. The ADC primarily supports a JESD204B interface that runs up to 12.8 Gbps and reduces the circuit-board routing challenges in high-channel count systems. The output interface of the ADC can also be set as a low-voltage differential signaling (LVDS) that can easily interface with low-cost field-programmable gate arrays (FPGAs). The ADC can operate at maximum speeds of 125 MSPS 16-bit and send out the digitized data with JESD204B interface. When the LVDS interface is used, the ADCs sampling rate and resolution are limited by the LVDS output rate of 1.28 Gbps, or 80 MSPS at 16-bit resolution. The ADC in 14-bit resolution can be configured in this scenario to sample at a higher speed but still maintain the same output data rate. The ADC is designed to scale its power with sampling rate.

The AFE58JD48 additionally includes a digital demodulator block. The digital in-phase and quadrature (I/Q) demodulator with programmable decimation filters accelerates computationally-intensive algorithms at low power.

The device also allows various power and noise combinations to be selected for optimizing system performance. Therefore, the device is a suitable ultrasound AFE solution for premium systems powered either by wall outlet or by batteries.

The device is available in a 15-mm × 15-mm NFBGA-289 package and is almost pin-compatible with the AFE58JD28 and AFE58JD18 devices.