SBASA64A December   2020  – June 2021 PCMD3140

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 6.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 6.10 Timing Requirements: PDM Digital Microphone Interface
    11. 6.11 Switching Characteristics: PDM Digial Microphone Interface
    12. 6.12 Timing Diagrams
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Reference Voltage
      4. 7.3.4 Microphone Bias
      5. 7.3.5 Digital PDM Microphone Record Channel
      6. 7.3.6 Signal-Chain Processing
        1. 7.3.6.1 Programmable Digital Volume Control
        2. 7.3.6.2 Programmable Channel Gain Calibration
        3. 7.3.6.3 Programmable Channel Phase Calibration
        4. 7.3.6.4 Programmable Digital High-Pass Filter
        5. 7.3.6.5 Programmable Digital Biquad Filters
        6. 7.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 7.3.6.7 Configurable Digital Decimation Filters
          1. 7.3.6.7.1 Linear Phase Filters
            1. 7.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 7.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 7.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 7.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 7.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 7.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 7.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 7.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 7.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 7.3.6.7.2 Low-Latency Filters
            1. 7.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 7.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 7.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 7.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 7.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 7.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 7.3.6.7.3 Ultra-Low-Latency Filters
            1. 7.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 7.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 7.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 7.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 7.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 7.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 7.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 7.3.7 Voice Activity Detection (VAD)
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode or Software Shutdown
      2. 7.4.2 Active Mode
      3. 7.4.3 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
    6. 7.6 Register Maps
      1. 7.6.1 Page 0 Registers
      2. 7.6.2 Page 1 Registers
      3. 7.6.3 Programmable Coefficient Registers
        1. 7.6.3.1 Programmable Coefficient Registers: Page 2
        2. 7.6.3.2 Programmable Coefficient Registers: Page 3
        3. 7.6.3.3 Programmable Coefficient Registers: Page 4
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Four-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.3.6.2 Programmable Channel Gain Calibration

Along with the programmable channel gain and digital volume, this device also provides programmable channel gain calibration. The gain of each channel can be finely calibrated or adjusted in steps of 0.1 dB for a range of –0.8-dB to 0.7-dB gain error. This adjustment is useful when trying to match the gain across channels resulting from external components and microphone sensitivity. This feature, in combination with the regular digital volume control, allows the gains across all channels to be matched for a wide gain error range with a resolution of 0.1 dB. Table 7-11 shows the programmable options available for the channel gain calibration.

Table 7-11 Channel Gain Calibration Programmable Settings
P0_R63_D[7:4] : CH1_GCAL[3:0] CHANNEL GAIN CALIBRATION SETTING FOR INPUT CHANNEL 1
0000 = 0d Input channel 1 gain calibration is set to –0.8 dB
0001 = 1d Input channel 1 gain calibration is set to –0.7 dB
… …
1000 = 8d (default) Input channel 1 gain calibration is set to 0 dB
… …
1110 = 14d Input channel 1 gain calibration is set to 0.6 dB
1111 = 15d Input channel 1 gain calibration is set to 0.7 dB

Similarly, the channel gain calibration setting for input channel 2 to channel 4 can be configured using the CH2_GCAL (P0_R68) to CH4_GCAL (P0_R78) register bits, respectively.