SBASA64A December 2020 – June 2021 PCMD3140
PRODUCTION DATA
This section provides a typical EVM I2C register control script that shows how to set up the PCMD3140 in a 4-channel digital PDM microphone recording mode.
# Key: w 9C XX YY ==> write to I2C address 0x9C, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the PCMD3140EVM user guide for jumper settings and audio connections.
#
# PDM 8-channel : PDMDIN1 - Ch1 and Ch2, PDMDIN2 - Ch3 and Ch4,
# PDMDIN3 - Ch5 and Ch6, PDMDIN4 - Ch7 and Ch8
# PDMCLKx = 2.8224 MHz (PDMCLKx/FSYNC = 64)
# FSYNC = 44.1 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Wait for 1ms.
#
# Wake-up device by I2C write into P0_R2 using internal AREG
w 9C 02 81
#
# Configure CH2_INSRC as Digital PDM Input by I2C write into P0_R65
w 9C 41 40
#
# Configure MICBIAS_GPI2 as Digital PDM Input by I2C write into P0_R59
w 9C 3B 70
#
# Configure GPO1 as PDMCLK by I2C write into P0_R34
w 9C 22 41
#
# Configure GPI1 and GPI2 as PDMDIN1 and PDMDIN2 by I2C write into P0_R43
w 9C 2B 45
#
# Enable Input Ch-1 to Ch-4 by I2C write into P0_R115
w 9C 73 F0
#
# Enable ASI Output Ch-1 to Ch-4 slots by I2C write into P0_R116
w 9C 74 F0
#
# Power-up ADC and PLL by I2C write into P0_R117
w 9C 75 60
#
# Apply FSYNC = 44.1 kHz and BCLK = 11.2896 MHz and
# Start recording data by host on ASI bus with TDM protocol 32-bits channel wordlength