SBASAG1A October   2021  – October 2024 ADC09DJ800 , ADC09QJ800 , ADC09SJ800

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Theory of Operation
          2. 6.3.2.4.2 ADC Core Calibration
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
      3. 6.3.3 Temperature Monitoring Diode
      4. 6.3.4 Timestamp
      5. 6.3.5 Clocking
        1. 6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 6.3.6 JESD204C Interface
        1. 6.3.6.1  Transport Layer
        2. 6.3.6.2  Scrambler
        3. 6.3.6.3  Link Layer
        4. 6.3.6.4  8B/10B Link Layer
          1. 6.3.6.4.1 Data Encoding (8B/10B)
          2. 6.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.6.4.3 Code Group Synchronization (CGS)
          4. 6.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.6.4.5 Frame and Multiframe Monitoring
        5. 6.3.6.5  64B/66B Link Layer
          1. 6.3.6.5.1 64B/66B Encoding
          2. 6.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.6.5.3 Initial Lane Alignment
          4. 6.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.6.6  Physical Layer
          1. 6.3.6.6.1 SerDes Pre-Emphasis
        7. 6.3.6.7  JESD204C Enable
        8. 6.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.6.9  Operation in Subclass 0 Systems
        10. 6.3.6.10 Alarm Monitoring
          1. 6.3.6.10.1 Clock Upset Detection
          2. 6.3.6.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode

Forward error correction (FEC) is an optional feature in JESD204C and is supported by ADC09xJ800. Whereas CRC-12 mode can only detect errors on the link, FEC is able to detect and correct errors in order to improve the bit error rate (BER) for error-sensitive applications. Many applications can tolerate random bit errors, however some applications, such as an oscilloscope, rely on long error-free measurements in order to detect a certain response from the device under test (DUT). An error in these applications may result in a false-positive detection of the response. Enable FEC mode by setting SHMODE to 2.

A scrambled multiblock of 32 blocks (2048 bits) is input into the FEC parity bit generator to generate the 26-bit parity word. The parity word is sent in the sync header stream of the next multiblock. The receiver then calculates its own 26-bit parity word and calculates the difference between the locally generated and received parity word, called the syndrome of the received bits. If the syndrome is 0, then all bits are assumed to have been received correctly, while any value other than 0 indicates at least one error in either the data bits or the parity word. If the syndrome is non-zero, then it can be used to determine the most likely error and then correct the error. The minimum latency from a bit error to detection and correct of a bit error in the first bit of a multiblock is 58 blocks.

The mapping of the sync header stream when using FEC mode is shown in Table 6-12. FEC[x] corresponds to bit x of the 26-bit FEC word. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is used to identify the end of a multiblock. It is possible for a 00001 sequence to appear in another location within the sync header stream in FEC mode, however it is improbable to see the 00001 sequence in the same location within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than one multiblock to find the end of a multiblock. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of an extended multiblock.

Table 6-12 Sync Header Stream Bit Mapping for FEC Mode
BitFunctionBitFunctionBitFunctionBitFunction
0FEC[25]8FEC[17]16FEC[9]24FEC[2]
1FEC[24]9FEC[16]17FEC[8]25FEC[1]
2FEC[23]10FEC[15]18FEC[7]26FEC[0]
3FEC[22]11FEC[14]19FEC[6]270
4FEC[21]12FEC[13]20FEC[5]280
5FEC[20]13FEC[12]21FEC[4]290
6FEC[19]14FEC[11]22EoEMB300
7FEC[18]15FEC[10]23FEC[3]311

The FEC encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 26-bit parity word using the generator polynomial given by Equation 11. The 2048 scrambled input bits plus 26 parity bits forms a shortened (2074, 2048) binary cyclic code. The (2074, 2048) binary cyclic code is shortened from the cyclic Fire code (8687, 8661). This polynomial can correct up to a 9-bit burst error per multiblock.

Equation 11. g(x) = (x17+1)(x9+x4+1) == x26+x21+x17+x9+x4+1

The full 26-bit FEC parity word generation is shown in Figure 6-10. The input is a 2048 bit sequence, built from the 32 scrambled blocks of a multiblock (sync header is not included). The 26-bit parity word, FEC[25:0], is taken from the Sx blocks after the full 2048 bit sequence is processed. The Sx blocks are initialized with 0s before processing each multiblock. For more information on the FEC parity word generation, refer to the JESD204C standard.

ADC09QJ800 ADC09DJ800 ADC09SJ800 FEC Parity Bit GeneratorFigure 6-10 FEC Parity Bit Generator

FEC decoding and error correction are not covered here. For full details on FEC decoding and error correction, refer to the JESD204C standard.