SBASAK4B March 2023 – April 2024 ADS127L21
PRODUCTION DATA
The device is reset through SPI operation by writing 01011000b to the CONTROL register. Writing any other value to this register does not result in a reset. In 4-wire SPI mode, reset takes effect at the end of the frame at the time CS is taken high. In 3-wire SPI mode, reset takes effect on the last falling edge of SCLK of the register write operation. Reset in 3-wire SPI mode requires that the SPI communication is synchronized to the host. If SPI synchronization is lost, use the pattern described in the Reset by SPI Input Pattern section to reset the device. Reset is validated by checking the POR_FLAG of the STATUS register.