SBASAK4B March   2023  – April 2024 ADS127L21

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 5.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 5.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 5.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Modulator
      5. 7.3.5 Digital Filter
        1. 7.3.5.1 Wideband Filter
          1. 7.3.5.1.1 Wideband Filter Options
          2. 7.3.5.1.2 Sinc5 Filter Stage
          3. 7.3.5.1.3 FIR1 Filter Stage
          4. 7.3.5.1.4 FIR2 Filter Stage
          5. 7.3.5.1.5 FIR3 Filter Stage
          6. 7.3.5.1.6 FIR3 Default Coefficients
          7. 7.3.5.1.7 IIR Filter Stage
            1. 7.3.5.1.7.1 IIR Filter Stability
        2. 7.3.5.2 Low-Latency Filter (Sinc)
          1. 7.3.5.2.1 Sinc3 and Sinc4 Filters
          2. 7.3.5.2.2 Sinc3 + Sinc1 and Sinc4 + Sinc1 Cascade Filter
      6. 7.3.6 Power Supplies
        1. 7.3.6.1 AVDD1 and AVSS
        2. 7.3.6.2 AVDD2
        3. 7.3.6.3 IOVDD
        4. 7.3.6.4 Power-On Reset (POR)
        5. 7.3.6.5 CAPA and CAPD
      7. 7.3.7 VCM Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Speed Modes
      2. 7.4.2 Idle Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
        1. 7.4.6.1 Synchronized Control Mode
        2. 7.4.6.2 Start/Stop Control Mode
        3. 7.4.6.3 One-Shot Control Mode
      7. 7.4.7 Conversion-Start Delay Time
      8. 7.4.8 Calibration
        1. 7.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        2. 7.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Fh, 10h, 11h)
        3. 7.4.8.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface (SPI)
        1. 7.5.1.1  Chip Select (CS)
        2. 7.5.1.2  Serial Clock (SCLK)
        3. 7.5.1.3  Serial Data Input (SDI)
        4. 7.5.1.4  Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.1.5  SPI Frame
        6. 7.5.1.6  Full-Duplex Operation
        7. 7.5.1.7  Device Commands
          1. 7.5.1.7.1 No-Operation
          2. 7.5.1.7.2 Read Register Command
          3. 7.5.1.7.3 Write Register Command
        8. 7.5.1.8  Read Conversion Data
          1. 7.5.1.8.1 Conversion Data
          2. 7.5.1.8.2 Data Ready
            1. 7.5.1.8.2.1 DRDY
            2. 7.5.1.8.2.2 SDO/DRDY
            3. 7.5.1.8.2.3 DRDY Bit
            4. 7.5.1.8.2.4 Clock Counting
          3. 7.5.1.8.3 STATUS Byte
        9. 7.5.1.9  Daisy-Chain Operation
        10. 7.5.1.10 3-Wire SPI Mode
          1. 7.5.1.10.1 3-Wire SPI Mode Frame Reset
        11. 7.5.1.11 SPI CRC
      2. 7.5.2 Register Memory CRC
        1. 7.5.2.1 Main Program Memory CRC
        2. 7.5.2.2 FIR Filter Coefficient CRC
        3. 7.5.2.3 IIR Filter Coefficient CRC
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SPI Operation
      2. 9.1.2 Input Driver
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Reference Voltage
      5. 9.1.5 Simultaneous-Sampling Systems
    2. 9.2 Typical Applications
      1. 9.2.1 A-Weighting Filter Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 PGA855 Programmable Gain Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 THS4551 Antialias Filter Design
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.1 Analog Input (AINP, AINN)

The analog input of the ADC is differential, with the input defined as a difference voltage: VIN = VAINP – VAINN. For best performance, drive the input with a differential signal with the common-mode voltage centered to mid-supply (AVDD1 + AVSS) / 2.

The ADC accepts either unipolar or bipolar input signals by configuring the AVDD1 and AVSS power supplies accordingly. Figure 7-1 shows an example of a differential signal with the supplies configured to unipolar operation. Symmetric input voltage headroom is available when the common-mode voltage is at mid-supply (AVDD1 / 2). Use AVDD1 = 5V and AVSS = 0V for unipolar operation (see specifications for reduced AVDD1 operation).

Figure 7-2 shows an example of a differential signal in bipolar operation. The common-mode voltage of the signal (VCM) is normally at 0V. Use AVDD1 = 2.5V and AVSS = –2.5V for bipolar operation.

GUID-49B583BB-45E2-4476-BD51-B5EB8CD466E1-low.gifFigure 7-1 Unipolar Differential Input Signal
GUID-B7FC401B-1ACC-4AED-AAB9-F7FC59B4E9E9-low.gifFigure 7-2 Bipolar Differential Input Signal

In either bipolar or unipolar power-supply configuration, the ADC accepts single-ended input signals by tying the AINN input to AVSS, ground, or mid-supply. However, because AINN is now fixed, the voltage range of the ADC is limited by the input voltage swing of AINP. That is, ±2.5V for bipolar operation or 0V to 5V for a 5V unipolar operation.

The simplified circuit shown in Figure 7-3 represents the analog input structure.

GUID-20220601-SS0I-XNWH-BKJS-GDX56TJPVCQW-low.svg Figure 7-3 Analog Input Circuit

Diodes protect the ADC inputs from electrostatic discharge (ESD) events. These events occur during the manufacturing process and during printed circuit board (PCB) assembly when manufactured in an ESD-controlled environment. If the inputs are driven below AVSS – 0.3V, or above AVDD1 + 0.3V, the protection diodes potentially conduct. If these conditions are possible, use external clamp diodes, series resistors, or both to limit the input current to the specified value.

The input multiplexer offers the option of normal or reverse input signal polarities. The multiplexer also provides two internal test modes to help verify ADC performance. The offset test mode verifies noise and offset error by providing a short to the ADC inputs. The resulting noise and offset voltage data are evaluated by the user. CMRR performance is tested using the CMRR test mode by applying a CMRR test signal to the AINP input. The resulting CMRR test data are also evaluated by the user. Table 7-1 shows the switch configurations of the input multiplexer circuit of Figure 7-3.

Table 7-1 Input Multiplexer Configurations
MUX[1:0] BITS CLOSED SWITCHES DESCRIPTION
00b S1, S4 Normal polarity input (VIN = VAINP - VAINN)
01b S2, S3 Reverse polarity input (VIN = VAINN - VAINP)
10b S5, S6 Internal noise and offset error test
11b S1, S5 CMRR test using a signal applied to AINP

The ADC samples the input voltage at the modulator frequency (fMOD) by storing the voltage on the CIN capacitor. The capacitor is discharged on the opposite clock phase of the modulator, at which time the sample process repeats. The instantaneous charge demand of CIN requires the signal to settle within a half cycle at the modulator frequency. This frequency is t = 1 / (2 · fMOD). To satisfy this requirement, the external driver bandwidth is typically required to be much larger than the original signal frequency. The bandwidth of the driver is determined sufficient when the desired THD, SNR, and gain error performance are achieved. In mid- and low-speed modes of operation, the modulator frequency is reduced, therefore more time is available for the driver to settle.

The input charge required by the sampling capacitor is modeled as a peak current and an average current flowing into the ADC inputs. As given in Equation 15 and Equation 16, the average input current is comprised of differential and absolute components.

Equation 15. Input Current (Differential Input Voltage) = fMOD · CIN · 106 (μA/V)

where:

  • fMOD = fCLK / 2
  • CIN = 7.4pF (1x input range), 3.6pF (2x input range)

Equation 16. Input Current (Absolute Input Voltage) = fMOD · CCM · 106 (μA/V)

where:

  • fMOD = fCLK / 2
  • CCM = 0.35pF (1x input range), 0.17pF (2x input range)

For fMOD = 12.8MHz (high-speed mode), CIN = 7.4pF, and CCM = 0.35pF, the average current resulting from the differential voltage is 95μA/V. The average current resulting from the absolute voltage is 4.5μA/V. For example, if AINP = 4.5V and AINN = 0.5V, then VIN = 4V. The total AINP average current = (4V · 95μA/V) + (4.5V · 4.5μA/V) = 400μA. The total AINN average current is (–4V · 95μA/V) + (0.5V · 4.5μA/V) = –378μA.

The device incorporates input precharge buffers to significantly reduce the charge demand from the CIN capacitor. When enabled, the buffers are initially in-circuit during the sampling phase. When CIN is nearly fully charged, the buffers are bypassed (S7 and S8 of Figure 7-3 in up positions). The external signal then provides the fine charge to the capacitor. At the completion of the sample phase, the sampling capacitor is discharged by the modulator to complete the conversion cycle. The buffers reduce the input current required to charge CIN, therefore improving the input impedance and relaxing external driver requirements. The input buffers are enabled by the AINP_BUF and AINN_BUF bits of the CONFIG1 register. If AINN is tied to ground or to a low-impedance fixed potential, disable the AINN buffer to reduce power consumption.