SBASAK4B March 2023 – April 2024 ADS127L21
PRODUCTION DATA
For external clock operation, program the CLK_SEL bit to 1b. Apply the clock signal to the CLK pin before programming the bit. A clock divider is available to divide the clock frequency. For example, divide a 25.6MHz clock signal by 8 to produce 3.2MHz internal clock for the low-speed mode.
Decrease the clock frequency to yield specific data rates between OSR values. However, when reducing the clock frequency, the conversion noise is the same as the original clock frequency. Reducing the conversion noise is only possible by increasing the OSR value or changing the filter mode.
Clock jitter results in timing variations when the signal is sampled, leading to degraded SNR performance. A low-jitter clock is essential to meet data sheet SNR performance. For example, with a 200kHz signal frequency, an external clock with <10ps (rms) jitter is required. For lower signal frequencies, the clock jitter requirement is relaxed by –20dB per decade of signal frequency. For example, with fIN = 20kHz, 100ps clock jitter is acceptable. Many types of RC oscillators exhibit high levels of jitter that are to be avoided for ac signal measurement. Instead, use crystal or bulk acoustic wave type oscillators. Avoid ringing on the clock input. A series resistor placed at the output of the clock buffer often helps reduce ringing.