SBASAK4B March   2023  – April 2024 ADS127L21

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 5.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 5.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 5.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Modulator
      5. 7.3.5 Digital Filter
        1. 7.3.5.1 Wideband Filter
          1. 7.3.5.1.1 Wideband Filter Options
          2. 7.3.5.1.2 Sinc5 Filter Stage
          3. 7.3.5.1.3 FIR1 Filter Stage
          4. 7.3.5.1.4 FIR2 Filter Stage
          5. 7.3.5.1.5 FIR3 Filter Stage
          6. 7.3.5.1.6 FIR3 Default Coefficients
          7. 7.3.5.1.7 IIR Filter Stage
            1. 7.3.5.1.7.1 IIR Filter Stability
        2. 7.3.5.2 Low-Latency Filter (Sinc)
          1. 7.3.5.2.1 Sinc3 and Sinc4 Filters
          2. 7.3.5.2.2 Sinc3 + Sinc1 and Sinc4 + Sinc1 Cascade Filter
      6. 7.3.6 Power Supplies
        1. 7.3.6.1 AVDD1 and AVSS
        2. 7.3.6.2 AVDD2
        3. 7.3.6.3 IOVDD
        4. 7.3.6.4 Power-On Reset (POR)
        5. 7.3.6.5 CAPA and CAPD
      7. 7.3.7 VCM Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Speed Modes
      2. 7.4.2 Idle Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
        1. 7.4.6.1 Synchronized Control Mode
        2. 7.4.6.2 Start/Stop Control Mode
        3. 7.4.6.3 One-Shot Control Mode
      7. 7.4.7 Conversion-Start Delay Time
      8. 7.4.8 Calibration
        1. 7.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        2. 7.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Fh, 10h, 11h)
        3. 7.4.8.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface (SPI)
        1. 7.5.1.1  Chip Select (CS)
        2. 7.5.1.2  Serial Clock (SCLK)
        3. 7.5.1.3  Serial Data Input (SDI)
        4. 7.5.1.4  Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.1.5  SPI Frame
        6. 7.5.1.6  Full-Duplex Operation
        7. 7.5.1.7  Device Commands
          1. 7.5.1.7.1 No-Operation
          2. 7.5.1.7.2 Read Register Command
          3. 7.5.1.7.3 Write Register Command
        8. 7.5.1.8  Read Conversion Data
          1. 7.5.1.8.1 Conversion Data
          2. 7.5.1.8.2 Data Ready
            1. 7.5.1.8.2.1 DRDY
            2. 7.5.1.8.2.2 SDO/DRDY
            3. 7.5.1.8.2.3 DRDY Bit
            4. 7.5.1.8.2.4 Clock Counting
          3. 7.5.1.8.3 STATUS Byte
        9. 7.5.1.9  Daisy-Chain Operation
        10. 7.5.1.10 3-Wire SPI Mode
          1. 7.5.1.10.1 3-Wire SPI Mode Frame Reset
        11. 7.5.1.11 SPI CRC
      2. 7.5.2 Register Memory CRC
        1. 7.5.2.1 Main Program Memory CRC
        2. 7.5.2.2 FIR Filter Coefficient CRC
        3. 7.5.2.3 IIR Filter Coefficient CRC
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SPI Operation
      2. 9.1.2 Input Driver
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Reference Voltage
      5. 9.1.5 Simultaneous-Sampling Systems
    2. 9.2 Typical Applications
      1. 9.2.1 A-Weighting Filter Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 PGA855 Programmable Gain Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 THS4551 Antialias Filter Design
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
7.3.5.1.6 FIR3 Default Coefficients

FIR3 coefficients are available without the need to supply custom coefficients. The default coefficients are selected by the FLTR_SEL[2:0] bits = 000b of the FILTER1 register. The default coefficients feature linear phase response, low pass-band ripple, narrow transition band, and high stop-band attenuation.

Figure 7-14 through Figure 7-18 illustrate the default wideband filter frequency response. Figure 7-14 shows the pass-band ripple. Figure 7-15 shows the frequency response at the transition band.

GUID-D0F983ED-FBCA-437C-98C4-5C70AA5077C2-low.gifFigure 7-14 Wideband Filter Pass-Band Ripple
GUID-067074CE-707B-4C08-8C51-D8CEE076C3F7-low.gifFigure 7-15 Wideband Filter Transition Band

Figure 7-16 illustrates the filter response up to fDATA for OSR ≥ 64. The stop band begins at fDATA / 2 to reduce signal aliasing. Figure 7-17 illustrates the filter to fMOD. In the stop-band region, signal frequencies intermodulate with multiples of the chop frequency at fMOD / 32. Thus, creating a series of response peaks that exceed the attenuation provided by the digital filter. The width of the response peaks is twice the filter bandwidth. Stop-band attenuation is improved when the ADC input is filtered by an analog antialias filter. See the Typical ApplicationsA-Weighting Filter DesignTHS4551 Antialias Filter Design section for details of a fourth-order antialias filter at the ADC input.

GUID-C26D6A6A-47C8-4D72-9B88-2DCAF2F86784-low.gif
OSR ≥ 64
Figure 7-16 Wideband Filter Frequency Response
GUID-A6877B55-2086-47B4-A3FA-A8F1E187CA91-low.svg
OSR = 32
Figure 7-17 Wideband Filter Stop-Band Attenuation

Figure 7-18 shows the filter response at fMOD. As shown, the filter response repeats for input signals at fMOD. If not removed by an antialias filter, signal frequencies at fMOD appear as aliased frequencies in the pass band.

GUID-CD8CB50A-BFD1-40D2-929F-D693F4564A52-low.svg Figure 7-18 Wideband Filter Frequency Response at fMOD

Aliasing also occurs with input frequencies occurring at multiples of fMOD. These frequency bands are defined by:

Equation 17. Alias frequency bands: (N · fMOD) ± fBW

where:

  • N = 1, 2, 3, and so on
  • fMOD = Modulator sampling frequency
  • fBW = Filter bandwidth

The group delay of the filter is the propagation time for an input signal to appear at the output of the filter. Because the filter is a linear-phase design, the envelope of a complex input signal is undistorted by the filter. The group delay (expressed in units of time) is constant versus frequency, equal to 34 / fDATA. After a step input is applied, fully settled data occur 68 data periods later. Figure 7-19 illustrates the filter group delay (34 / fDATA) and the settling time to a step input (68 / fDATA).

GUID-749D9496-5FE3-4000-8FC6-4926F4EC97E5-low.svg Figure 7-19 Wideband Filter Step Response

The digital filter is restarted when the ADC is synchronized. The ADC suppresses the first 68 conversion periods until the filter is fully settled. There is no need to discard data after synchronization. The time of data suppression is the conversion latency time as listed in the latency time column of Table 7-12. Sixteen fCLK cycles of overhead time are incurred for all data rates. If a step input is applied randomly to the conversion period without synchronizing, the next 69 conversions are unsettled data. The –0.1dB frequency of the amplitude response is 0.4125 × fDATA and the –3dB frequency is 0.4374 × fDATA for all data rates.

Table 7-7 Wideband Default Filter Characteristics
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 –0.1dB FREQUENCY
(kHz)		 –3dB FREQUENCY
(kHz)		 LATENCY TIME(3)
(µs)
Max speed 32.768 32 512 211.2 223.9 135.5
High speed 25.6 400 165 174.96 173.4
Mid speed 12.8 200 82.5 87.48 346.9
Low speed 3.2 50 20.63 21.87 1387.8
Max speed 32.768 64 256 105.6 112.0 270.4
High speed 25.6 200 82.5 87.48 346.1
Mid speed 12.8 100 41.25 43.74 692.2
Low speed 3.2 25 10.31 10.94 2768.7
Max speed 32.768 128 128 52.8 55.99 540.0
High speed 25.6 100 41.25 43.74 691.2
Mid speed 12.8 50 20.63 21.87 1382.3
Low speed 3.2 12.5 5.1562 5.468 5529.2
Max speed 32.768 256 64 26.4 28.00 1079.2
High speed 25.6 50 20.625 21.87 1381.3
Mid speed 12.8 25 10.31 10.93 2762.6
Low speed 3.2 6.25 2.578 2.734 11051
Max speed 32.768 512 32 13.2 14.00 2157.6
High speed 25.6 25 10.312 10.935 2761.6
Mid speed 12.8 12.5 5.156 5.467 5523.3
Low speed 3.2 3.125 1.289 1.367 22093
Max speed 32.768 1024 16 6.6 7.998 4314.2
High speed 25.6 12.5 5.156 5.467 5522.3
Mid speed 12.8 6.25 2.578 2.734 11045
Low speed 3.2 1.5625 0.645 0.6834 44178
Max speed 32.768 2048 8 3.3 3.499 8627.8
High speed 25.6 6.25 2.578 2.734 11044
Mid speed 12.8 3.125 1.289 1.367 22087
Low speed 3.2 0.78125 0.322 0.3417 88348
Max speed 32.768 4096 4 1.65 1.750 17254
High speed 25.6 3.125 1.289 1.367 22086
Mid speed 12.8 1.5625 0.645 0.6834 44172
Low speed 3.2 0.390625 0.161 0.1709 176690
(3) IIR filter bypassed. Latency time increases by 8 / fCLK (μs) when analog input buffers are enabled.