SBASAK4B March   2023  – April 2024 ADS127L21

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 5.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 5.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 5.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Modulator
      5. 7.3.5 Digital Filter
        1. 7.3.5.1 Wideband Filter
          1. 7.3.5.1.1 Wideband Filter Options
          2. 7.3.5.1.2 Sinc5 Filter Stage
          3. 7.3.5.1.3 FIR1 Filter Stage
          4. 7.3.5.1.4 FIR2 Filter Stage
          5. 7.3.5.1.5 FIR3 Filter Stage
          6. 7.3.5.1.6 FIR3 Default Coefficients
          7. 7.3.5.1.7 IIR Filter Stage
            1. 7.3.5.1.7.1 IIR Filter Stability
        2. 7.3.5.2 Low-Latency Filter (Sinc)
          1. 7.3.5.2.1 Sinc3 and Sinc4 Filters
          2. 7.3.5.2.2 Sinc3 + Sinc1 and Sinc4 + Sinc1 Cascade Filter
      6. 7.3.6 Power Supplies
        1. 7.3.6.1 AVDD1 and AVSS
        2. 7.3.6.2 AVDD2
        3. 7.3.6.3 IOVDD
        4. 7.3.6.4 Power-On Reset (POR)
        5. 7.3.6.5 CAPA and CAPD
      7. 7.3.7 VCM Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Speed Modes
      2. 7.4.2 Idle Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
        1. 7.4.6.1 Synchronized Control Mode
        2. 7.4.6.2 Start/Stop Control Mode
        3. 7.4.6.3 One-Shot Control Mode
      7. 7.4.7 Conversion-Start Delay Time
      8. 7.4.8 Calibration
        1. 7.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        2. 7.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Fh, 10h, 11h)
        3. 7.4.8.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface (SPI)
        1. 7.5.1.1  Chip Select (CS)
        2. 7.5.1.2  Serial Clock (SCLK)
        3. 7.5.1.3  Serial Data Input (SDI)
        4. 7.5.1.4  Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.1.5  SPI Frame
        6. 7.5.1.6  Full-Duplex Operation
        7. 7.5.1.7  Device Commands
          1. 7.5.1.7.1 No-Operation
          2. 7.5.1.7.2 Read Register Command
          3. 7.5.1.7.3 Write Register Command
        8. 7.5.1.8  Read Conversion Data
          1. 7.5.1.8.1 Conversion Data
          2. 7.5.1.8.2 Data Ready
            1. 7.5.1.8.2.1 DRDY
            2. 7.5.1.8.2.2 SDO/DRDY
            3. 7.5.1.8.2.3 DRDY Bit
            4. 7.5.1.8.2.4 Clock Counting
          3. 7.5.1.8.3 STATUS Byte
        9. 7.5.1.9  Daisy-Chain Operation
        10. 7.5.1.10 3-Wire SPI Mode
          1. 7.5.1.10.1 3-Wire SPI Mode Frame Reset
        11. 7.5.1.11 SPI CRC
      2. 7.5.2 Register Memory CRC
        1. 7.5.2.1 Main Program Memory CRC
        2. 7.5.2.2 FIR Filter Coefficient CRC
        3. 7.5.2.3 IIR Filter Coefficient CRC
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SPI Operation
      2. 9.1.2 Input Driver
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Reference Voltage
      5. 9.1.5 Simultaneous-Sampling Systems
    2. 9.2 Typical Applications
      1. 9.2.1 A-Weighting Filter Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 PGA855 Programmable Gain Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 THS4551 Antialias Filter Design
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD1 =  5 V, AVDD2 = 1.8 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VIN = 0 V, VCM = 2.5 V, VREFP =  4.096 V, VREFN = 0 V, high-reference range, 1x input range, all speed modes, input precharge buffers on, and reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS, MAX-SPEED MODE
Input current,
differential input voltage		 Precharge buffers off 125 µA/V
Precharge buffers off, 2x input range 60
Precharge buffers on ±4 µA
Input current drift,
differential input voltage		 Precharge buffers off 5 nA/V/°C
Precharge buffers off, 2x input range 2
Precharge buffers on 5 nA/°C
Input current,
common-mode input voltage		 Precharge buffers off 6.5 µA/V
Precharge buffers off, 2x input range 3
Precharge buffers on ±4 µA
ANALOG INPUTS, HIGH-SPEED MODE
Input current,
differential input voltage		 Precharge buffers off 95 µA/V
Precharge buffers off, 2x input range 47
Precharge buffers on ±3 µA
Input current drift,
differential input voltage		 Precharge buffers off 3 nA/V/°C
Precharge buffers off, 2x input range 1.5
Precharge buffers on 5 nA/°C
Input current,
common-mode input voltage		 Precharge buffers off 5 µA/V
Precharge buffers off, 2x input range 2.5
Precharge buffers on ±3 µA
ANALOG INPUTS, MID-SPEED MODE
Input current,
differential input voltage		 Precharge buffers off 47 µA/V
Precharge buffers off, 2x input range 25
Precharge buffers on ±1.5 µA
Input current drift,
differential input voltage		 Precharge buffers off 2 nA/V/°C
Precharge buffers off, 2x input range 1
Precharge buffers on 5 nA/°C
Input current,
common-mode input voltage		 Precharge buffers off 2.5 µA/V
Precharge buffers off, 2x input range 1.3
Precharge buffers on ±1.5 µA
ANALOG INPUTS, LOW-SPEED MODE
Input current,
differential input voltage		 Precharge buffers off 12 µA/V
Precharge buffers off, 2x input range 6
Precharge buffers on ±0.4 µA
Input current drift,
differential input voltage		 Precharge buffers off 1 nA/V/°C
Precharge buffers off, 2x input range 0.5
Precharge buffers on 0.2 nA/°C
Input current,
common-mode input voltage		 Precharge buffers off 0.6 µA/V
Precharge buffers off, 2x input range 0.3
Precharge buffers on ±0.4 µA
DC PERFORMANCE
Resolution OSR ≥ 32 24 Bits
Noise See the Noise Performance section for details
INL Integral nonlinearity (1)
 TA = 25°C ± 5°C 0.4 1.4 ppm of FSR
TA = 0°C to 70°C 0.4 1.8
TA = –40°C to 125°C 0.4 2.2
Max-speed mode 1.5
Offset error TA = 25°C –250 ±30 250 µV
Offset drift 50 200 nV/°C
Offset long-term drift 1000 hr 0.5 µV
Gain error TA = 25°C –2500 ±200 2500 ppm of FSR
Gain drift 0.5 1 ppm of FSR/°C
Gain long-term drift 1000 hr 10 ppm
NMRR Normal-mode rejection ratio fIN = 50 Hz (±1 Hz), fDATA = 50 SPS, sinc4 filter 100 dB
fIN = 60 Hz (±1 Hz), fDATA = 60 SPS, sinc4 filter 100
CMRR Common-mode rejection ratio At dc 110 130 dB
Up to 10 kHz 115
At dc, 2x input range 95
PSRR Power-supply rejection ratio AVDD1, dc 100 120 dB
AVDD2, dc 115 130
IOVDD, dc 115 130
AC PERFORMANCE, MAX-SPEED MODE (fCLK = 32.768 MHz)
fDATA Data rate Full wideband filter 4 512 kSPS
FIR2 wideband filter 8 1024
FIR1 wideband filter 16 2048
Low-latency filter 0.1024 1365.3
DR Dynamic range Inputs shorted,
OSR = 64, fDATA = 256 kSPS		 Wideband filter 109 111.5 dB
Wideband filter,
VREF = 2.5 V		 107.5
Wideband filter,
VREF = 2.5 V,
2x input range		 108.5
Sinc4 filter 112 114
Sinc4 filter,
VREF = 2.5 V		 110.5
Sinc4 filter,
VREF = 2.5 V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1 kHz, VIN = –0.2 dBFS,
OSR = 64, fDATA = 256 kSPS
 		 Wideband filter 110 dB
Wideband filter,
VREF  = 2.5 V		 106
Wideband filter,
VREF  = 2.5 V,
2x input range		 107
Sinc4 filter 112
Sinc4 filter,
VREF = 2.5 V		 108.5
Sinc4 filter
VREF = 2.5 V,
2x input range		 110
THD Total harmonic distortion fIN = 1 kHz, VIN = –0.2 dBFS
OSR = 64, fDATA = 256 kSPS		 VREF  = 2.5 V –119 –108 dB
VREF  = 4.096 V –110 –103
IMD Intermodulation distortion fIN = 9.7 kHz and 10.3 kHz,
VIN = –6.5 dBFS		 Second-order terms –125 dB
Third-order terms –120
SFDR Spurious-free dynamic range fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64 110 dB
AC PERFORMANCE, HIGH-SPEED MODE (fCLK = 25.6 MHz)
fDATA Data rate Full wideband filter 3.125 400 kSPS
FIR2 wideband filter 6.25 800
FIR1 wideband filter 12.5 1600
Low-latency filter 0.08 1067
DR Dynamic range Inputs shorted,
OSR = 64, fDATA = 200 kSPS		 Wideband filter 109 111.5 dB
Wideband filter,
VREF = 2.5 V		 107.5
Wideband filter,
VREF = 2.5 V,
2x input range		 108.5
Sinc4 filter 112 114.5
Sinc4 filter,
VREF = 2.5 V		 110.5
Sinc4 filter,
VREF = 2.5 V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1 kHz, VIN = –0.2 dBFS,
OSR = 64, fDATA = 200 kSPS
 		 Wideband filter 110 dB
Wideband filter,
VREF = 2.5 V		 106
Wideband filter,
VREF = 2.5 V,
2x input range		 107
Sinc4 filter 112
Sinc4 filter,
VREF = 2.5 V		 108.5
Sinc4 filter,
VREF = 2.5 V,
2x input range		 110
THD Total harmonic distortion fIN = 1 kHz, VIN = –0.2 dBFS,
OSR = 64, fDATA = 200 kSPS		 VREF = 2.5 V –125 -113 dB
VREF = 4.096 V –125 -106
IMD Intermodulation distortion fIN = 9.7 kHz and 10.3 kHz,
VIN =  –6.5 dBFS		 Second-order terms –125 dB
Third-order terms –125 dB
SFDR Spurious-free dynamic range fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64 125 dB
AC PERFORMANCE, MID-SPEED MODE (fCLK = 12.8 MHz)
fDATA Data rate Full wideband filter 1.5625 200 kSPS
FIR2 wideband filter 3.125 400
FIR1 wideband filter 6.25 800
Low-latency filter 0.08 533.3
DR Dynamic range Inputs shorted,
OSR = 64, fDATA = 100 kSPS		 Wideband filter 109 112 dB
Wideband filter,
VREF = 2.5 V		 107.5
Wideband filter,
VREF = 2.5 V
2x input range		 108.5
Sinc4 filter 112 114.5
Sinc4 filter,
VREF = 2.5 V		 110.5
Sinc4 filter,
VREF = 2.5 V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1 kHz, VIN = –0.2 dBFS,
OSR = 64, fDATA = 100 kSPS
 		 Wideband filter 110 dB
Wideband filter,
VREF = 2.5 V		 106
Wideband filter,
VREF = 2.5 V,
2x input range		 107
Sinc4 filter 112
Sinc4 filter,
VREF = 2.5 V		 108.5
Sinc4 filter,
VREF = 2.5 V,
2x input range		 110
THD Total harmonic distortion fIN = 1 kHz, VIN = –0.2 dBFS,
OSR = 64, fDATA = 100 kSPS		 VREF = 2.5 V –125 –117 dB
VREF = 4.096 V –125 –115
IMD Intermodulation distortion fIN = 9.7 kHz and 10.3 kHz,
VIN = –6.5 dBFS		 Second-order terms –125 dB
Third-order terms –125
SFDR Spurious-free dynamic range fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64 125 dB
AC PERFORMANCE, LOW-SPEED MODE (fCLK = 3.2 MHz)
fDATA Data rate Full wideband filter 0.390625 50 kSPS
FIR2 wideband filter 0.78125 100
FIR1 wideband filter 1.5625 200
Low-latency filter 0.01 133.3
DR Dynamic range Inputs shorted,
OSR = 64, fDATA = 25 kSPS		 Wideband filter 109 112 dB
Wideband filter,
VREF = 2.5 V		 107.5
Wideband filter,
VREF = 2.5 V,
2x input range		 108.5
Sinc4 filter 112 114.5
Sinc4 filter,
VREF = 2.5 V		 110.5
Sinc4 filter,
VREF = 2.5 V,
2x input range		 111.5
SNR Signal-to-noise ratio fIN = 1 kHz, VIN = –0.2 dBFS,
OSR = 64, fDATA = 25 kSPS		 Wideband filter 110 dB
Wideband filter,
VREF = 2.5 V		 106
Wideband filter,
VREF = 2.5 V,
2x input range		 108
Sinc4 filter 112
Sinc4 filter,
VREF = 2.5 V		 108
Sinc4 filter,
VREF = 2.5 V,
2x input range		 110
THD Total harmonic distortion fIN = 1 kHz, VIN = –0.2 dBFS,
OSR = 64, fDATA = 25 kSPS		 VREF = 2.5 V –125 –114 dB
VREF = 4.096 V –125 –113
IMD Intermodulation distortion fIN = 9.7 kHz and 10.3 kHz,
VIN = –6.5 dBFS		 Second-order terms –125 dB
Third-order terms –125 dB
SFDR Spurious-free dynamic range fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64 125 dB
DEFAULT FIR FILTER
Pass-band frequency Within envelope of pass-band ripple 0.4 ∙ fDATA Hz
–0.1-dB frequency 0.4125 ∙ fDATA
–3-dB frequency 0.4374 ∙ fDATA
Pass-band ripple –0.0004 0.0004 dB
Stop-band frequency At stop-band attenuation 0.5 · fDATA Hz
Stop-band attenuation(2) 106 dB
Group delay 34 / fDATA s
Settling time 68 / fDATA s
Overall decimation ratio 8 4096
PROGRAMMABLE FIR3 FILTER
Number of taps 128
Coefficient resolution 32 bits
Coefficient format 1.31
Decimal range –1 1 – 1/231
Decimation ratio 2
PROGRAMMABLE IIR FILTER
Implementation Four biquads, direct form 1
Scale factors 5
Coefficient resolution 32 bits
Coefficient format 2.30
Decimal range –2 2 – 2/231
Decimation ratio 1
VOLTAGE REFERENCE INPUTS
REFP and REFN input current REFP precharge buffer off Max-speed mode 225 µA/V
High-speed mode 190
Mid-speed mode 130
Low-speed mode 80
REFP input current REFP precharge buffer on ±2 µA
REFP and REFN
input current drift		 REFP precharge buffer off Max-speed mode 10 nA/℃
High-speed mode 10
Mid-speed mode 10
Low-speed mode 10
REFP input current drift REFP precharge buffer on 10 nA/℃
INTERNAL OSCILLATOR
Frequency 25.4 25.6 25.8 MHz
VCM OUTPUT VOLTAGE
Output voltage (AVDD1 + AVSS) / 2 V
Accuracy –1% ±0.1% 1%
Voltage noise 1-kHz bandwidth 25 µVRMS
Start-up time CL = 100 nF 1 ms
Capacitive load 100 nF
Resistive load 2 kΩ
Short-circuit current limit 10 mA
DIGITAL INPUTS/OUTPUTS
VIL Logic-low input threshold 0.3 IOVDD V
VIH Logic-high input threshold 0.7 IOVDD V
Input hysteresis 150 mV
Input current Excluding RESET pin –1 1 µA
RESET pin pullup resistor 20 kΩ
VOL Logic-low output voltage OUT_DRV = 0b, IOL = 2 mA 0.2 ∙ IOVDD V
OUT_DRV = 1b, IOL = 1 mA 0.2 ∙ IOVDD
VOH Logic-high output voltage OUT_DRV = 0b, IOH = –2 mA 0.8 ∙ IOVDD V
OUT_DRV = 1b, IOH = –1 mA 0.8 ∙ IOVDD
ANALOG SUPPLY CURRENT
IAVDD1, IAVSS AVDD1 and AVSS current
(buffers off)		 Max-speed mode 2.1 2.2 mA
High-speed mode 1.7 1.8
Mid-speed mode 0.9 1.0
Low-speed mode 0.25 0.3
Standby mode 35 µA
Power-down mode 5
AVDD1 and AVSS additional
current (per buffer function)		 Input precharge buffer Max-speed mode 1.75 2.3 mA
High-speed mode 1.35 1.9
Mid-speed mode 0.7 1.0
Low-speed mode 0.2 0.3
REFP precharge buffer Max-speed mode 1.8 1.95 mA
High-speed mode 1.5 1.6
Mid-speed mode 0.9 1.0
Low-speed mode 0.4 0.5
VCM buffer 0.1 mA
IAVDD2, IAVSS AVDD2 and AVSS current Max-speed mode 4.5 4.9 mA
High-speed mode 3.5 3.8
Mid-speed mode 2.2 2.5
Low-speed mode 0.85 0.95
Standby mode 60 µA
Power-down mode 1
DIGITAL SUPPLY CURRENT
IIOVDD IOVDD current
 		 Wideband filter, OSR = 32,
IIR filter off		 Max-speed mode 7.2 8.5 mA
High-speed mode 5.7 6.8
Mid-speed mode 2.8 3.4
Low-speed mode 0.75 0.9
Low-latency filter, OSR = 32
 		 Max-speed mode 1.1 1.3 mA
High-speed mode 0.85 1.0
Mid-speed mode 0.45 0.55
Low-speed mode 0.15 0.18
Standby mode External clock 10 µA
Internal oscillator 40
Power-down mode 10 µA
IOVDD additional current IIR filter on, OSR = 32,
High-speed mode		 FIR/IIR sequence 0.3 mA
IIR/FIR sequence 0.6
POWER DISSIPATION
PD Power dissipation AVDD2 = 1.8 V,
Precharge buffers off,
IIR and FIR filters, OSR = 32		 Max-speed mode 32.8 mW
High-speed mode 26
Mid-speed mode 14
Low-speed mode 4.3
AVDD2 = 1.8 V,
Precharge buffers off,
Low-latency filter, OSR = 32		 Max-speed mode 20.6 mW
High-speed mode 16.3
Mid-speed mode 9.3
Low-speed mode 3.1
(1) Best-fit method.
(2) Stop-band attenuation as provided by the digital filter. Input frequencies in the stop band intermodulate with multiples of the chop frequency beginning at fMOD / 32, which results in stop-band attenuation exceeding 106 dB. See the Stop-Band Attenuation figure for details.