11 Revision History
Changes from Revision * (March 2024) to Revision A (June 2024)
- Changed data port Features bulletGo
- Changed discussion of frame-sync data port in Description
sectionGo
- Changed ADS127L14 pin numbering in the Pin Configurations and Functions
sectionGo
- Changed CLKIN timing requirementsGo
- Changed START pin timing requirements Go
- Changed Timing Diagrams sectionGo
- Changed the Data Averaging sectionGo
- Changed ADS127L14 register map CRC range from registers (08h to 30h)
to (08h to 50h)Go
- Changed FSYNC Pin sectionGo
- Changed DCLK Pin sectionGo
- Changed the Time Division Multiplexing sectionGo
- Changed Daisy Chain sectionGo
- Changed Data Packet sectionGo
- Changed Data Port Timing Adjustment sectionGo
- Changed DP_TDM[1:0] description in DP_CFG1 registerGo
- Changed ADS127L14 CRC register map range from registers (08h to 30h) to (08h to
50h)Go
- Changed ADS127L14 SPI address range error from register (30h) to
(50h)Go
- Changed Amplitude peaking to Pass-band amplitude peaking in
Antialias Filter Design Requirements tableGo
- Changed which ADS127L14 AVSS pin numbers do not need bypass
capacitors in Power Supply Recommendations
Go