SBASAM0A March 2024 – June 2024 ADS127L18
ADVANCE INFORMATION
The frame-sync data port outputs the channel conversion data. The port is a synchronous, read-only interface with synchronized output clock signals (FSYNC and DCLK) and channel data (DOUTn) for reading by an external controller. The frame-sync signals are continuously operated except when stopped and restarted in the start/stop control mode.
Figure 7-30 shows the frame-sync pins. Pins 8 through 13 of the frame-sync port are multiplexed with GPIO pins. When enabled, the GPIO function takes priority over the frame-sync pins. Default mode is all GPIO off.
Figure 7-31 shows the timing of the frame-sync port (DIN and GPIO functions are subsequently removed from the pin names). New channel data are synchronized on the FSYNC rising edges, where the data bits update on the DCLK falling edges. The dependent fields shown in the figure are data that depends on the time division multiplexing option.